EDA

May 25, 2022

Siemens brings ReadyStart RTOS to RISC-V

Siemens has expanded its Nucleus ReadyStart program to the RISC-V architecture.
Article  |  Topics: Blog - Embedded  |  Tags: , , , ,   |  Organizations:
April 29, 2022

Navigate variables and lifetimes in SystemVerilog

Variable lifetimes are an apparently basic but also tricky feature within the verification language.
Article  |  Topics: Verification  |  Tags: , , , , ,   |  Organizations: ,
April 28, 2022

Go inside proposals for common chiplet models

Chiplets will need models to guarantee heterogenous SiP implementation. A cross-industry working group describes its progress so far.
April 27, 2022

Verifying the new namespace storage options in NVMe 2.0

The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , ,   |  Organizations:
March 13, 2022

Learn strategies for better measurement and test in simulation-based PCB design

A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
Article  |  Topics: Blog - PCB  |  Tags: , , , , ,   |  Organizations:
March 4, 2022

Verification engineers look to better skills to beat schedules

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , ,
March 2, 2022

Synopsys talks AI in verification at DVCon

Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
February 10, 2022

Capturing connectivity for assembly verification in 2.5D and 3D design

Learn how to ingest data from multiple engineering teams in multiple formats on interposer and other multi-dimensional projects.
Article  |  Topics: Verification  |  Tags: , , , , , , , , ,   |  Organizations:
February 8, 2022

How digital twin evaluations optimize STCO-based design

System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
January 25, 2022

Silicon Photonics verification case study from UC-Davis and Texas A&M

Silicon Photonics 3D integration posed LVS challenges in this fast emerging technical space. A case study describes how the two institutions overcame them.
Article  |  Topics: Verification  |  Tags: , ,   |  Organizations: , ,

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