EDA

September 27, 2022

Siemens automates test to handle multi-die 2.5D, 3D and 5.5D architectures

Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
Article  |  Topics: EDA - DFT  |  Tags: , , , , , , , , , ,   |  Organizations:
September 21, 2022

Agile Analog adds digital library for easier porting

Agile Analog has launched its own digital standard cell library, designed to be used in the control circuits for analog blocks that form the IP company’s main offering.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations:
September 15, 2022

Cadence extends AI to verification data with unified database

Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
September 8, 2022

Module verification demands integrated DRC and LVS

The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
September 8, 2022

Use equivalence checking to retarget obsolete FPGA designs

Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
September 5, 2022

Parasitic extraction challenges intensify for 5G

5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , , , , , ,   |  Organizations:
September 5, 2022

Cybersecurity must be built in not bolted on

Learn how one of the leading tool vendors addresses the security of its products and customer data through a ground-up cybersecurity strategy.
Article  |  Topics: Blog - EDA, - HLS, Tool development  |  Tags: , , , ,   |  Organizations:
August 31, 2022

Intel and partners join for RISC-V development push

Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
August 3, 2022

Imperas releases RISC-V coverage library as open source

Imperas Software has published an open-source functional-coverage library for RISC-V cores.
July 18, 2022

Open-source EDA grapples with the incentives issue

As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.

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