EDA

September 11, 2019

Embedded design meets low-code in Siemens integration plans

Siemens is combining recent acquisitions in novel ways, including one that will see a web-app development package interact more closely with Mentor's embedded offerings.
Article  |  Topics: Blog - Embedded, PCB  |  Tags: , , , ,   |  Organizations: ,
September 10, 2019

Digital twin points the way to system-level vehicle safety

The digital-twin concept provides several avenues to achieving better safety analysis and is likely to benefit from Siemens' integration of Mentor activities.
Article  |  Topics: Blog - Embedded, IP, PCB  |  Tags: , , , , ,   |  Organizations: ,
September 3, 2019
Joe Sawicki, EVP for IC EDA, Mentor. 'AI inside' analysis

EDA with ‘AI inside’ – Mentor’s Joe Sawicki offers an insider’s view

Mentor has a host of tools - some public, some not - that leverage AI and ML. EVP Joe Sawicki has been describing the strategy behind their development.
August 27, 2019

How to achieve faster, more relevant early-stage DRC with Recon

The new Calibre Reconnaissance feature within Mentor's physical verification suite aims to maximize compute resources and deliver manageable reports.
Article  |  Topics: Digital/analog implementation, Verification  |  Tags: , , , , , , , ,   |  Organizations:
August 23, 2019

Making the case for HLS in autonomous drive

The automotive market faces challenges that make it a prime candidate for the greater use of high-level synthesis on designs with AI and ML content.
August 15, 2019

Optimized DRC in the cloud

A new whitepaper describes some of the techniques you can use to get the most out of cloud-based DRC with Calibre.
August 6, 2019

Increased cooperation seen as vital for automotive safety verification

Safety verification calls for increased collaboration across the supply chain, experts say. The challenge is finding ways to make that happen.
July 27, 2019

A repeatable methodology for modern reset domain crossing issues

Reset domain crossing is another area where rising SoC complexity and IP reuse is causing an increase in reliability and safety challenges.
July 11, 2019

C++ signoff made real

Konica Minolta describes how it has constructed a C++ signoff flow that mitigates code ambiguity, manual analysis and other inefficiencies.
Article  |  Topics: Blog - EDA, - HLS, Verification  |  Tags: , , , ,   |  Organizations: ,
July 8, 2019

Coventor updates process simulation tool

Coventor has updated its SEMulator virtual-fab tool and added the ability to tune process windows based on simulation results.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors