The formal apps start-up has built strong positions in automotive and RISC-V and will strengthen Siemens in competition with Cadence.
The vendor has reworked its website and discussed more about its strategy going forward, following its rebranding from Mentor.
Siemens has introduced a cloud-based DFM tool intended to bridge the gap between the electronics design and manufacturing.
Cadence Design Systems has designed a new custom processor for the Z2 emulator and employed Xiliinx UltraScale+ for the prototyping platform.
Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.
Siemens Digital Industries Software has launched the latest generation of its Veloce hardware-assisted verification systems with a product line that encompasses silicon virtual platform, hardware emulation, and prototyping support.
The best paper awards at this month's DVCon highlighted techniques to streamline verification. The European version in the meantime is looking for paper submissions.
At the recent Embedded World show and conference, Colin Walls of Siemens tackled the choices facing software developers working with multicore SoCs.
Following its rebranding from Mentor, the division will have a strong presence in the main program and across virtual roundtables at next week's online event.
A new white paper reviews the history of the open-source platform and provides guidance on best practice development for embedded.
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