EDA

July 26, 2021

Learn how to apply formal verification to safety-critical aviation designs

A detailed technical overview of formal verification within the context of the DO-254 (ED-80) standard is now available to download.
Article  |  Topics: Verification  |  Tags: , , , , , , ,   |  Organizations:
July 22, 2021

Cadence uses reinforcement learning to tune flow

Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
Article  |  Topics: Blog - EDA  |  Tags: , , ,   |  Organizations:
July 16, 2021

How to meet formal embedded software guidance for medical devices

Vulnerabilities in connected healthcare products have led medical requlators to issue further security recommendations for their design and maintenance.
Article  |  Topics: Blog - Embedded  |  Tags: , , , , ,   |  Organizations: ,
June 21, 2021

From iterative to in-design DRC and debug for place and route

Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
June 17, 2021

Standard arrives for thermal simulation data

A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
May 28, 2021

Would you prefer a hypervisor or a multicore framework?

Determining which embedded technique to adopt is more than just a question of what cores the system has.
May 28, 2021

PCIe 6.0 gets verification IP as formal arrival approaches

Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Article  |  Topics: Blog - EDA, IP, - Verification  |  Tags: , , , , , , ,   |  Organizations: ,
May 21, 2021

Cadence pushes its FastSpice to 32 cores

Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
Article  |  Topics: Blog - EDA  |  Tags: , ,   |  Organizations:
May 19, 2021

Understand how DO-254 defines verification for avionics

The avionics design assurance guidance has its own flavor of verification which needs to be understood alongside its definition of validation.
May 14, 2021

How MaxLinear cut physical verification time with in-design DRC

A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.

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