EDA

Real Intent has developed a tool for identifying potential security issues in chip designs at the sign-off stage.

Mil/aero specialist Abaco Systems refined its workflow across multiple design sites after the pandemic constrained collaboration.

PCB routing is best served by a mixture of manual and automated tasks. A new e-book describes the boundaries between the two.

The flat nature of traditional IC packaging design struggles to cope with the chiplet era. Homogeneous disaggregation offers an alternative.

The technique is becoming increasingly important for designs that need to be flexible, compact and lightweight.

DTCO (design technology co-optimization) looks to address systemic verification challenges but the process still needs to be extended.

Make it easier to capture issues in 2.5D and 3D designs with multiple chiplets and emerging challenges with this 'shift left' approach.

How the various features within today's Calibre physical verification family help designers shift left tasks and cut time-to-market.

Certification to ISO 26262 for automotive systems and compatibility with the latest Arm9 generation of processors and the CHI-E interface are among the updates to Arteris’ Ncore cache-coherent on-chip network IP framework.

Arm is working with Cadence and Siemens on separate projects to support its plans in the SDV space.