Real Intent tool looks for glitches
Real Intent has turned its attention to the verification of connectivity and the potential for circuits to glitch, starting at RTL and taking that through to netlist-level signoff.
When using the SafeConnect tool design and verification engineers can define rules for various source-destination types to help enable low-noise reporting. Real Intent claims its approach to analysis will work out to be ten times faster than formal solutions coupled with TcL-based scripting and provides integration with its debug tool.
The company sees the tool being deployed in two main scenarios. The first is during RTL design to check memory, power, and debug logic connectivity as well as to ensure circuitry is designed to avoid glitches on user-specified asynchronous, multicycle, and false paths. Designers can also avoid improper connectivity that can lead to block abutment issues during layout.
The second scenario is post-synthesis, with checks on the same paths on the resulting netlist. At this stage, engineers can find and address new issues such as improper power supply rail crossing or incorrect DFT logic connectivity.
As well as supporting user-defined checks, users can take advantage of a readymade set of documented checks. Some representative rules that customers have created include retention reset and clock correctness, glitch propagation, test-logic multiplexer and debug-bus checks, and abutment verification. SafeConnect also allows more granular sub-checks to help reduce noise in the violation reports. Examples of sub-checks are cross connect, source miss, extra connection, and bit flip. The tool also accepts UPF as direct input to help speed up specification generation.
Black boxing is available, but is not required for large designs, the company claimed, and the tool can be run on any design type, including designs with complex control logic and clock gating.
