How to meet formal embedded software guidance for medical devices
Vulnerabilities in connected healthcare products have led medical requlators to issue further security recommendations for their design and maintenance.
EDA
From iterative to in-design DRC and debug for place and route
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
Standard arrives for thermal simulation data
A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
Would you prefer a hypervisor or a multicore framework?
Determining which embedded technique to adopt is more than just a question of what cores the system has.
PCIe 6.0 gets verification IP as formal arrival approaches
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
Cadence pushes its FastSpice to 32 cores
Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
Understand how DO-254 defines verification for avionics
The avionics design assurance guidance has its own flavor of verification which needs to be understood alongside its definition of validation.
How MaxLinear cut physical verification time with in-design DRC
A case study describes how the RF and AMS specialist achieved efficiencies on a complex server DSP SoC project by running as-you-go DRC during place and route.
Sigasi editor provided free for open-source hardware developers
Sigasi aims to attract developers working on open-source projects with a version of its Studio suite the company is making available for free to that community.
Siemens extends Solido’s reach into IP validation with Fractal
Latest acquisition adds technologies to mitigate rising verification time and cost for third-party IP.
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