Parasitic extraction challenges intensify for 5G
Parasitic extraction challenges for ICs targeting 5G mobile networks have been raised by a number of factors.
Meeting the growing standard’s speed, bandwidth, latency and reliability requirements has raised the bar across elements such as converters, oscillators, amps and PLLs, requiring aggressive innovation. Various low power and RF requirements have also driven greater use of fully-depleted silicon-on-insulator (FD-SOI) processes.
A recently white paper from Siemens EDA, ‘Parasitic extraction challenges and solutions for 5G IC design‘, provides a comprehensive description of the various challenges designers face and shows how they can be automated and managed by using the Calibre xACT platform.
“While shrinking device sizes and finer line widths allow IC designers to pack more functionality onto a chip, the tighter spacing also generates more parasitics that must be understood and managed,” explain authors Karen Chow and Salma Ahmed Elhenedy.
“As dimensions get smaller, interactions not only increase between transistors, but also between transistors and interconnects. These interactions become key factors affecting signal delay and other circuit performance metrics.”
They highlight issues around the use of metal-insulator-metal (MIM) and metal-oxide-metal (MOM) capacitors as one of a number of examples where parasitic extraction for 5G demands is particularly tricky.
“Engineers can implement symmetric plate design with high-capacity density (due to minimum width and spacing for metals) that doesn’t compromise the frequency characterization, enabling the layout to achieve the circuit quality set in the design specifications. MIM/MOM capacitors also deliver good matching characteristics, due to lateral coupling,” they write. “However, the extensive use of MIM/MOM capacitors in 5G designs can present a number of PEX challenges, caused by sensitivity to process variations that affect capacitive accuracy, such as metal and dielectric layer thickness, metal widths, and other variations of process parameters over the wafer.
Another section takes a dive into the issues presented by layers and well when a design targets an FD-SOI process: “Because there are multiple base layers, with the substrate at different heights, the idea of a parasitic capacitor to ‘ground’ gets more complicated, because where is the ground? Is it the higher ground, or the lower ground?”
To find out more, the paper is available for download here.
