Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.
Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
Virtual prototyping case study focuses on address mapping, clocking and QoS in DDR memory interface optimisation
Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
Cadence is creating a flow that the company believes will make it possible to bring greater predictability to photonics design.
HyperLynx from Mentor Graphics has moved into a new generation with more integrated features beyond PI and SI, and an easier to use GUI.
View All Sponsors