simulation

October 29, 2019

Circuit analysis speed up radiation checks for automotive SoCs

Optima DA has launched a family of tools designed to speed up the analysis of radiation susceptibility in automotive SoC designs.
October 7, 2019

Master the design and verification of next gen transport: Part Four – emulation

Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
May 23, 2019

AI and ML fuel Catapult and Calibre updates

Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
February 19, 2019

DVCon USA 2019 preview: SmartDV

The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
Article  |  Topics: Conferences, Verification  |  Tags: , , ,   |  Organizations: ,
November 7, 2018

Symphony raises crescendo for AMS simulation

Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
May 1, 2018

Andes teams with Imperas and UltrasoC for RISC-V

Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
February 12, 2018

DVCon US 2018 preview: Mentor

The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
March 2, 2017

How formal concentrates ISO 26262 fault analysis

Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.
February 27, 2017

Cadence tunes up simulators and FPGA prototyping

Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
January 10, 2017

Virtual prototyping case study focuses on address mapping, clocking and QoS in DDR memory interface optimisation

Case study applies virtual prototyping to optimise address mapping, clock frequency, and Quality of Service configurations to meet DDR performance goals.
Article  |  Topics: ESL/SystemC, Product  |  Tags: , ,   |  Organizations:

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