Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
Optima DA has launched a family of tools designed to speed up the analysis of radiation susceptibility in automotive SoC designs.
Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
The Siemens subsidiary is involved with a wide range of tutorials, technical papers and more at this month's San Jose conference.
Formal enables substantial fault pruning and more definitive fault injection for ISO 26262 using techniques such as sequential logic equivalence checking.
Cadence has reworked two parts of its verification suite to streamline the use of multicore computers for simulation and FPGA-based prototyping systems.
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