Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
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MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.
Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.
MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
Cadence has used machine-learning techniques originally developed for its Cerebrus tool to build software that can speed up multiphysics analysis.
Synopsys and Analog Devices have agreed to provide model libraries for the chipmaker's DC/DC ICs and power regulators that work with the Saber simulation tool.
A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
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