Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
DAC provided a forum for the growing number of verification efforts focused on checking the architectural compliance and overall RTL quality of RISC-V processors.
Deadlock is hard to detect even though there are formal strategies for doing so. But wouldn't it be better if you could automate that work? Now you can.
Optima DA has launched a family of tools designed to speed up the analysis of radiation susceptibility in automotive SoC designs.
Emulation is already playing a vital role in advanced automotive design within a digital twin environment.
Mentor takes the wraps off new machine learning fueled features in its HLS and physical design families ahead of DAC 2019.
The verification IP specialist is focusing on its new products for RISC-V verification and for emulation platforms next week in San Jose.
Mentor's updated AMS platform claims performance boost by obviating 'legacy' technology.
Andes Technology has expanded support for its RISC-V processor cores through deals with Imperas and UltraSoC.
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