simulation

June 28, 2022

Aachen spinout claims fastest RISC-V simulator

MachineWare claims it can reach 2GHz throughput with instruction-set simulator for RISC-V processors.
June 10, 2022

Cadence adds machine learning to electrical simulation

Cadence has used machine-learning techniques originally developed for its Cerebrus tool to build software that can speed up multiphysics analysis.
Article  |  Topics: Blog - EDA, Electrical Design  |  Tags: , , ,   |  Organizations:
May 24, 2022

Saber models aim for ADI power chips

Synopsys and Analog Devices have agreed to provide model libraries for the chipmaker's DC/DC ICs and power regulators that work with the Saber simulation tool.
Article  |  Topics: Blog - IP  |  Tags: , ,   |  Organizations: ,
March 13, 2022

Learn strategies for better measurement and test in simulation-based PCB design

A new white paper offers useful tips and techniques for PDN analysis and performance optimization in designs such as those using DDR4.
Article  |  Topics: Blog - PCB  |  Tags: , , , , ,   |  Organizations:
March 2, 2022

Synopsys talks AI in verification at DVCon

Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
November 3, 2021

Python provides the link for speed checks at Sondrel

Sondrel has combined EDA tools with custom SystemC and Python code to develop a system that can help automate the detailed performance analysis of high-level architectures before RTL is generated.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , , ,   |  Organizations: ,
March 29, 2021

OpenHW gets free simulator from Imperas

Imperas Software has released a free instruction set simulator that covers the OpenHW Group's implementations of the RISC-V processor architecture.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , ,   |  Organizations: ,
November 3, 2020

Showing ‘equivalence’ to seed digital twin adoption

A partnership between Siemens and VSI, a real-world autonomous vehicle research company, aims to refine and promote digital twin strategies.
Article  |  Topics: Digital Twin, Verification  |  Tags: , , , , , , ,   |  Organizations:
August 17, 2020

Cadence uses machine learning to trim constrained-random runtimes

Cadence has developed a stimulus optimizer based on neural networks to try to improve the runtime of constrained-random verification runs.
Article  |  Topics: Blog - EDA  |  Tags: , , , ,   |  Organizations:
July 31, 2020

Open-RAN puts more focus on emulation in testing programs

Recent developments have made Open-RAN look more attractive as a way of implementing 5G systems. This is helping to drive a shift-left in verification and test.
Article  |  Topics: Blog - EDA, IP, PCB  |  Tags: , , , , , ,   |  Organizations:

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