SPIE Advanced Lithography 2018 preview: Mentor

By TDF Staff |  No Comments  |  Posted: February 16, 2018
Topics/Categories: Conferences, Design to Silicon  |  Tags: , , , , , , ,  | Organizations: ,

Mentor, a Siemens business, will focus on its latest innovations for EUV and OPC technologies during SPIE Advanced Lithography 2018. SPIE is taking place from February 25 to March 1 at the San Jose Convention Center in San Jose.

The Mentor booth (#222) will focus on these areas in particular:

EUV readiness

  • SRAF requirements, relevance, and impact on EUV lithography for next-generation processes beyond the 7nm node
  • Model-based hyper-NA anamorphic EUV OPC
  • The impact of aberrations in EUV lithography: metal to via edge placement control

 OPC approaches for memory applications and flows

  • Model-based cell-array OPC for improving the productivity of memory fabrication
  • The application of model-assisted template extraction techniques to contact hole patterns in high-end flash memory device fabrication

Mentor’s participation across the SPIE technical conference is also extensive. In addition to the events listed below, you can also find out more about the company’s activities at its dedicated SPIE landing page.

SPIE Advanced Lithrography Conference Sessions

Tuesday, February 27

  • SRAF requirements, relevance, and impact on EUV lithography for next-generation beyond 7nm node (1:30pm, Room 220A)
  • Model-based hyper-NA anamorphic EUV OPC (2:10pm, Room 220A)
  • Impact of aberrations in EUV lithography: metal to via edge placement control (2:30pm, Room 220A)

 

Wednesday, February 28

  • Constraint approaches for some inverse lithography problems with pixel-based mask (9:10am, Room 210C)
  • Model-based cell-array OPC for productivity improvement in memory fabrication (10:30am, Room 210C)
  • Model-assisted template extraction application to contact hole patterns in high-end flash memory device fabrication (11:10am, Room 210C)
  • A model-based approach for the scattering-bar printing avoidance (2:30pm, Room 210C)
  • A novel processing platform for post tape out flows (2:50pm, Room 210C)

 

Thursday, March 1

  • Combinational optical rule check on hotspot detection (11:30am, Room 211B)
  • Integrated manufacturing flow for selective-etching SADP/SAQP (2:20pm, Room 211)
  • Comparison between traditional SADP/SAQP and selective-etching SADP/SAQP (2:45pm, Room 211)

 

SPIE Advanced Lithography Poster Sessions

Tuesday, February 27

5:30pm-7:30pm, Hall 2
  • Exploring EUV and SAQP pattering schemes at 5nm technology node
  • Ultimate patterning limits for EUV at 5nm node and beyond

 

Wednesday, February 28

5.30pm-7.30pm, Hall 2
  • A novel method to fast fix the post OPC weak-points through Calibre eqDRC application
  • Inverse lithography recipe optimization using genetic algorithm
  • Cross-MEEF assisted SRAF print avoidance approach
  • A weak pattern random creation method for lithography process tuning
  • A smart way to extract repeated structures of a layout
  • Using pattern-based layout comparison for a quick analysis of design changes
  • An efficient way of layout processing based on Calibre DRC and pattern matching for defects inspection application
  • Leverage Calibre pattern matching to address SRAM verification challenges at advanced nodes

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