Fujimura asks EDA to bend towards manufacturability

By Chris Edwards |  No Comments  |  Posted: July 11, 2022
Topics/Categories: Blog - EDA  |  Tags: , , , , , , , ,  | Organizations: ,

For a long time, Aki Fujimura has been keen on breaking chip design out of Manhattan routing and rectilinear shapes. Two decades ago, he was instrumental in driving the concept of the X Architecture in which routers would have 45° routes open to them in order to shorten overall distances and cut the number of bias.

In practice, delays to the introduction of EUV lithography made it increasingly difficult to deploy even if tools were reconfigured to support the angled routes. Multiple patterning relied on routing structures more like grating patterns with vertical and horizontal routes split across metal layers. According to Fujimura, ten chips taped out using the approach.

Today, as the head of D2S, which now specializes in software running on GPUs to handle mask generation, said at DAC he sees a brighter future Fujimura for a seemingly more radical change though one that is perhaps counter-intuitively more compatible with the realities of lithography in the nanometre era. E-beam has some attributes that make curved and irregular shapes not only relatively easy to draw but makes them potentially more desirable than they are today. To some extent, chipmakers have accepted that circular shapes are inevitable. Take via contacts, for example, which despite being represented in layout software as square are accepted as circular by the time they appear on the surface of the die. Is there any point in trying to Manhattanise these shapes? Not really.

Rather than just accept the circular shapes appearing, Fujimura reckons designers can go further and embrace curvilinear layouts on the understanding this will improve performance on the final wafer. D2S is not alone. Imec presented work in 2019 that showed dealing with curved shapes in design that would more closely resemble what’s printed on the mask rather than trying to compensate for the fuzzing effects of lithography and etching on shapes with sharp angles could be used to produce more compact cell designs that demonstrate lower loads and interconnect delays. Work by Micron showed that curved shapes improve process windows and reduce overall manufacturing variability and, in turn, better yield. Micron has also used curvilinear shapes to manually define jogs in multibit data lines on memory devices, with each jog having a slightly different angle and contour to improve overall density.

Reworking design

There are, naturally, issues in making curvilinear masks workable. One is at the design end and will require EDA vendors possibly change the way their tools handle layout and design-rules checks.

“I’m not coming from the manufacturing side totally naïve to design considerations,” Fujimura said. “I’m seeing a unique convergence of interests where we can do both design and manufacturing become much better by doing curvilinear design.”

The other is in manufacturing. But here, D2S is more optimistic that things are going its way. The equipment is not exactly where you might want it for maximum penetration though Fujimura said it is available where it is most likely to be used: the leading edge.

The road to curvilinear masks started with the development of variable-shape electron-beam (VSB) tools that are able to dynamically alter the size and shape of the pulses they fire at the mask as it is created. Though this makes curvilinear designs feasible it does not mean they are cheap. If the aim is maximum fidelity then write time increases significantly as the tool attempts to stitch together smooth curves from successive small shots. However, with 193nm immersion lithography, D2S has found this is not required: the resolution of 193nm simply is not good enough to need it. This allows the use mask-wafer co-optimisation where the use of inverse lithography – a computationally intensive operation that DS2 tries to solve using GPU acceleration – works out the minimum number of shots needed to create the intended curvilinear shapes.

This step is less necessary with the newer multibeam tools and though D2S has looked closely at technique to improve VSB throughput on curved shapes, Fujimura now takes the view that multibeam will be main target. Because a multibeam writer behaves more like a pixel-based display, there is no effective write-time overhead, just that of defining the curvilinear rather than the Manhattan shapes that have been through optical proximity correction (OPC). The curvilinear masks may in fact be simpler than one produced using the conventional OPC-based approach. EUV’s higher resolution means MWCO is less productive and may call into question the need to use curvilinear shapes. However, D2S is working on the assumption that improved depth of field, which was demonstrated in the earliest work on curvilinear mask shapes by Samsung and Luminescent more than a decade ago, will see chipmakers want to use the technique and, in turn, take advantage of density optimizations that defining standard cells and other details are curved shapes may offer.

Time for R&D

Fujimura said he understands it will take time to build an infrastructure in EDA around curvilinear, and put up a listing for a dream DAC 2025 track that covered academic R&D on the approach. He pointed to four main tool segments that will need support for curvilinear to be built for widespread use. Custom design is a key element as those tools will be required to develop standard cells tuned for the approach. Another is routing, if manufacturers choose to employ curvilinear techniques to make wide buses easier to layout. Fujimura pointed to the work Micron did manually on wide buses as a key example. For logic, automated routers able to go off the grid would be needed as attempting to do this by hand is far too time-consuming, assuming there is an advantage on certain metal layers to use those kinds of jogs. If the arbitrary jogs help vias or reduce wirelength significantly, that may well be the case.

The other key tools are parasitic extraction, which already have to cope with 3D elements already though they might need to rework meshes to handle high densities of curved objects. The other is design rule checking (DRC) but Siemens is embracing the concept and has already had to deal with curved shapes for photonics design. In a blog post for the company, John Sturtevant wrote: “The Calibre team is actively developing solutions to unlock the advantages of CL and to deal with some of the accompanying challenges. We have developed a suite of efficient mask MPC, OPC, and verification solutions that will help in the transition to curvilinear masks, whether for intrinsically curvilinear patterns needed in Silicon Photonics, or what we have ’traditionally’ viewed as rectilinear designs for logic or memory.”

Though it is not entirely clear whether curvilinear will be more important within cells or routing between them – particularly in a world where the finest routing layers are more like diffraction gratings – Fujimura is confident the value is there. “I do think power, performance and area will all improve.”

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