Research center IMEC and Cadence Design Systems have taped out the layout for a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
According to Vassilios Gerousis, distinguished engineer at Cadence, the aim of the metal-only test chip is to analyze the performance of EUV and 193nm immersion (193i) on the most critical metal layers – layers two (M2) and three (M3) as well as the lowest level of via contacts (V1) – which will have pitches ranging from 36nm down to 24nm.
Praveen Raghavan, principal scientist at IMEC, said the aim is to explore three approaches to defining the metal layers. The team used a processor design, with accompanying SRAM, as the source of the interconnect features that will be implemented on the test chip.
The first approach will use self-aligned quadruple patterning (SAQP) for the M2 and M3 interconnect lines, with 193i used to define the cuts. The vias will also use multiple exposures under 193i.
The second technique to be tried will again employ SAQP for the metal lines but with EUV for the cuts and vias. The third will use only EUV, removing the need to use cut masks for M2 and M3.
To define the metal layers, Cadence developed optimized design rules, libraries and place-and-route technology for the target process using its Innovus Implementation System. The company says the software uses parallel processing to speed up design and provide more computation power to deliver improved power, performance and area (PPA) characteristics.
“Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, senior vice president of process technology at imec. “Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. The Cadence next-generation platform is easy to use, which helps our engineering team stay productive in developing the rule set for advanced nodes.”