Layout schema generation speeds early-stage yield learning
LSG generates random design-like test vehicles to enable more detailed pre-ramp analysis for incoming nodes.
immersion lithography
Cadence and Imec tape out 3nm interconnect test chip
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
IMEC 5nm test chip to explore EUV and SAQP litho options
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
imec and Coventor partner for 7nm process development
Process development alliance will enable Imec to experiment on 10 and 7nm processes in the computer before moving to the fab
TSMC: e-beam winning on cost over EUV for lithography
EUV may be getting most R&D cash but the world's biggest foundry says e-beam currently has the edge on defects and double patterning.
Gartner: Multi-patterning here to stay, EUV lithography still 50:50
Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group
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