SPIE Advanced Lithography preview: Mentor Graphics

By TDF Staff |  No Comments  |  Posted: February 13, 2017
Topics/Categories: Blog Topics, Conferences, Design to Silicon, Blog - EDA  |  Tags: , , , , , , , , ,  | Organizations: , , , , , ,

The SPIE Advanced Lithography conference begins in just under two weeks on Sunday, February 26 and runs until Thursday, March 2 at the San Jose Convention Center. Mentor Graphics experts will be delivering conference papers, post sessions, and answering engineers’ questions in Booth #221.

After 42 years, lithography continues to be a hot topic for the semiconductor industry. There are seven separate conferences at this year’s event featuring hundreds of technical papers and posters, plus courses, the exhibition hall, plenary presentations, and social events.

Specific topics at SPIE Advanced Lithography extend well past mask synthesis and RET/OPC into DFM, design enablement, emerging technologies, and design-technology co-optimization.

Mentor is represented in the technical area with 10 papers and 10 posters. You can download its full list of technical presentations here. The company’s presence this year emphasizes its research on emerging technologies, including directed self-assembly (DSA) and multi-patterning.

Mentor will also be promoting its deep partnerships in lithography with both leading-edge foundries and university research groups.

Mentor Graphics and foundry partners at SPIE Advanced Lithography

On the foundry front, Mentor has collaborated on a number of papers at SPIE Advanced Lithography that demonstrates the widespread usage and application of its Calibre tools. Key partners and presentations include:

  • Samsung
    • “Interlayer verification methodology for multi-patterning processes” (March 1, 9:50am, Rm 210B).
    • “FinFET-induced anisotropy in printing of implantation shapes” (March 2, 11:35am, Rm 210C).
    • “Early-stage hotspot analysis through standard cell base random pattern generation” (March 2, 3:40pm, Rm 220C).
  • GlobalFoundries
    • “Enhanced OPC recipe coverage and early hotspot detection through automated layout generation and analysis” (March 1, 3:20pm, Rm 210C).
    • “Directed self-assembly (DSA) of Lamella-type of copolymers in self-aligned via (SAV) application from design to patterning” (March 1, 4:10pm, Rm Marriott San Jose Salon III).
    • “Effective use of aerial image metrology for calibration of OPC models” (March 2, 8:40am, Rm 210C).
  • SMIC
    • “Lithography and OPC friendly triple patterning decomposition method for via” (March 1, Poster Session).
    • “A random approach of pattern library creation for full chip litho-simulation” (March 1 Poster Session).
    • “Layout decomposition and analysis using pattern matching” (March 1, Poster Session).
    • “A flexible and efficient way to set-up QA system based on pattern database management” (March 1, Poster Session).
    • “An efficient way of layout processing based on pattern matching for defects inspection application” (March 1, Poster Session).
    • “A fast and efficient method for device level layout analysis” (March 1, Poster Session).
  • STMicroelectronics
    • “Si-photonics waveguides manufacturability using advanced RET solutions” (March 2, 9:40am, Rm 210C).
  • Shanghai Huali Microelectronics Corp
    • “Litho hotspots fixing using model-based algorithm” (March 1, Poster Session).

Mentor Graphics and academic partners at SPIE Advanced Lithography

Mentor’s relationship with the academic community is also represented in the SPIE Advanced Lithography program. Co-authors on major papers at the conference are:

  • The University of Texas at Austin
    • “Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices” (February 28, 2:20pm, Rm 210B).
    • “Model-based guiding pattern synthesis for on target and robust assembly of via and contact layers using DSA” (February 28, Poster Session).
  • Institute of Microelectronics (China)/University of Electronic Science and Technology of China
    • “Hotspots fixing flow in NTD process by using DTCO methodology at 10nm metal 1 layer” (March 1, Poster Session).

If you are involved in design for manufacturing or post-tapeout engineering, SPIE Advanced Lithography is a key date on the annual calendar. For more details on this year’s program and registration, click here.

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