VLSI to explore vertical device changes and 3nm finFET

Intel will describe its 3nm-node finFET process at the VLSI Symposium on Technology and Circuits in Hawaii in mid-June alongside papers from a variety of semiconductor organisations that investigate the viability of backside contacts and power distribution, and novel memory technologies.

Intel expects its latest finFET process to provide a 10% area reduction for logic reduction over Intel 4, as well as an improvements of around 15% in performance, through a combination of design-technology co-optimization, and transistor and interconnect changes. Though designed for higher-density logic, the process will support 1.2V I/O transistors and cater for long-channel analog devices. The company also expects an improvement in reliability.

At the upcoming conference, Samsung Electronics is involved with two papers that examine the use of backside technologies to improve IC density. In one, the company demonstrates a stacked FET with backside gate contacts in an attempt to show that logic can scale beyond the 1nm node. A joint paper with IBM focuses on the nearer-term prospects for power interconnect to the backside of the wafer and how process decisions will affect average cell density. They found direct backside contact-based schemes offer the best cell level scaling compared to other options. The joint team will describe a novel self-aligned backside contact scheme integrated with nanosheet transistors that offers immunity to misalignments when the backside contacts are formed.

A paper from Imec will examine how thermal considerations will play into PPA for both nanosheet and future stacked FETs based on the institute’s CFET architecture. Using a many-core processor based on an open-source design, the researchers found that in scaling from nanosheet at the A10 node to CFET at A5, the design should exhibit a 2.5% increase in Fmax, a 25% reduction in power, and a 35% area reduction. That would lead to an increase in power density of 15% under nominal condition of 0.7 V and 25 °C.

Thermal analysis indicated that a reduction of 64mV in Vdd and 10% in frequency would be required for transistors at the A5 node to maintain the same maximum junction temperature as those built on the A10 node operating at 0.7 V. The reduction in voltage and speed should, however, still result in a 40% gain in system throughput.

The conference takes place in Honolulu from June 16 to 20, 2024.