POCV


May 2, 2018

TSMC certifies Synopsys tool flow for 7nm EUV process

New flow enables high-performance, high-integration designs.
Article  |  Topics: Blog - EDA, - Product  |  Tags: , ,   |  Organizations: ,
April 6, 2017

Solido sets up lab to drive machine-learning adoption

Solido aims to bring the types of machine-learning techniques the company has used for its physical-analysis tools to a wider range of EDA tools through the launch of its ML Labs initiative.
April 16, 2014

FinFET variability issues challenge advantages of new process

Managing finFET variability issues without extending design times is key to extracting the most from the new processes, key players told a panel at the recent SNUG meeting in Santa Clara.
Article  |  Topics: Conferences, Blog - EDA  |  Tags: , , , , ,   |  Organizations: , , , ,
June 4, 2013

Timing signoff: maybe it’s time to get rid of the clock

The effort needed in timing signoff could lead to a shift in design towards asynchronous techniques unless advanced OCV technologies improve.

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