Micron sees NAND powering on as DRAM struggles

By Chris Edwards |  No Comments  |  Posted: June 20, 2018
Topics/Categories: Blog - EDA, IP  |  Tags: , , , , ,  | Organizations:

Despite the intense R&D going into storage-class and other novel forms of non-volatile memories, flash is set to continue as the bulk memory of choice, claimed Scott DeBoer, technology development executive vice president at Micron Technology, in his keynote at VLSI Symposia this week (19 June, 2018) in Hawaii.

For the moment, the news is not so good for DRAM because looks to be running into the same scaling wall as planar NAND was several years ago. But changes in architecture could keep DRAM scaling for a little while longer if it stays a purely 2D memory.

“NAND is going to hold down the lowest cost per bit for the foreseeable future,” DeBoer claimed and also pointed to the emergence of higher-performance variants that may close off opportunities for novel storage-class memories. He added: “DRAM is hitting scaling walls. Some of us have alaready seen this with planar NAND. DRAM is now heading down the same path on conventional scaling. The industry is making some progresss but still it’s slowing.

“There are two possible paths. One is to come back with a different DRAM architecture,” DeBoer said, pointing to the prior shift from an 8F2 cell structure to 6F2. “The second path is to identify a new memory with the same attributes. It is an effort that lots of people are focused on.”

According to DeBoer, DRAM makers are now looking at process and materials options to find other scaling paths for the technology now that factors such as the aspect ratio of the capacitor, which has risen “from the one over 10s-ish to one over 35” challenge the capability of etching technology.

Memory catchup

DeBoer said, in general, memory development has failed to keep pace with the requirements of today’s leading end-user products, particularly the smartphone. This is likely to spur novel approaches to integration, he argued.

“Smartphones are going to continue to require larger and faster memory systems, whether it’s for running more artificial intelligence on the edge or an obvious applications like 5G or higher resolution graphics. All those things combine to be a very demanding perspective of what memory has to deliver.

“The phone has become what the computer was [20 years ago]. The phone is absolutely driving memory innovation. This is the thing we are marching to to deliver better memory solutions.”

DeBoer added: “One of the main constraints is on bandwidth. The inherent memory bandwidth is actually quite high. The limitation of how it talks to the processor is the bandwidth of the bus. This leads to thoughts about application-specific memory.”

One response from the memory makers has been to use packaging technology such as HBM. It has a catch, DeBoer said: “It fits into only certain kinds of applications because of its cost.” That limits the use of HBM to markets such as server-based training for AI, although DeBoer sees server AI as being a turning into a huge market over the next decade. He pointed to projections that indicate AI-enabled servers will be responsible for almost half the data-center population by 2025, rising from around 10 per cent in 2021. “We are looking at an explosion in the data economy,” he said, which will be largely driven in a “virtuous circle” by machine-learning technology.

Processing migration

In portable markets, DeBoer said there is likely to be a greater focus on moving processing closer to memory and creating products that instead of simply sending data to a processor incorporate APIs so they can use higher on-chip or in-package bandwidth to support local manipulation.

In the near term, memory makers such as Micron are wrestling with choices over how to tweak line widths and other process options to move beyond DRAM’s 1Y generation. For DeBoer, this means more extensive use of multiple patterning rather than EUV.

“Pattern multiplication is a technology that revolutionized the industry’s ability to scale beyond 40nm. This technology by itself enabled NAND scaling through the last planar generations,” DeBoer explained. Similarly, for DRAM, “EUV is not a requirement. At this time EUV doesn’t make sense from a capability point of view in the DRAM space.”

DeBoer said an analyis of the cost of using EUV versus pattern multiplication pointed to quadruple patterning proving to be lower cost down to a line spacing of 10nm. To move further, EUV itself would be significantly more expensive and require double patterning itself. “People say ‘quadruple patterning, that must be expensive’,” he noted, “But it isnt’. But I know it’s a different case for logic.”

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