Cadence’s path to digital implementation on 10nm
The 10nm process will see changes to multiple patterning that demands changes in the implementation flow, along with an increased focus on the effects of variability.
In September, Cadence Design Systems achieved certification for its digital, custom/analog and signoff tools from TSMC for v0.9 of the upcoming 10nm finFET process, and is on track to achieve V1.0 completion by Q4 2015. The certification is part of a program to ensure that the EDA tools will handle the 10nm process in an efficient and effective manner to provide the best PPA results.
The development and certification processes will in turn enable systems and semiconductor companies to deliver advanced-node designs to market faster for mobile phones, tablets, application processors, and high-end servers.
Jonathan Smith, Cadence technical marketing director, says: “One key element of the 10nm development program was to accommodate the need for more complex multipatterning scenarios than those encountered at the 14nm, 16nm, and 20nm nodes.
“The main difference between 14/16nm and 10nm is that there are more patterning layers. Quadruple patterning is beginning to come into play.”
Foundries are faced with choices as to what combination of multiple patterning steps offer the best tradeoffs between design flexibility and device yield and performance. Each device and interconnect layer has its own characteristics that may favor, for example, repeated litho-etch over self-aligned multiple patterning. The decision will affect the design rules that are needed to ensure correct coloring at each layer.
“Whatever the foundries use, we will support it. And we do it on the fly in the flow,” Smith says, noting: “Some are doing it after the fact.”
On the 14nm/16nm nodes, coloring analysis was less important at the design stage. Libraries and design rules could be used that allowed coloring to be performed with high effectiveness during back-end mask-making processes. The need to move from double patterning to multiple patterning brings with it the requirement to handle mask coloring in digital designs at a much earlier stage.
“We believe that it will be impossible to do after the fact. It needs to be done on the fly. The place-and-route tool has to understand the coloring. That’s a must now,” Smith says.
As well as the coloring choice for each device or interconnect element, multiple patterning results in increased variability and extraction issues. Smith says: “Early extraction on the fly is also a must. You need signoff accuracy moved earlier in the flow.”
Smith points to the increase in parasitics such as wire resistance as well as the more complex electrical environment around the 3D structure of the finFET itself. “At 10nm wire resistance is an incredibly significant effect. We may need to move some of the interconnect path to wires in the upper layers, which offer lower resistance, so it becomes a design-optimization requirement. Much lower operating voltages also increase the sensitivity of delay calculation. These factors all become part of the logic-synthesis and place-and-route optimization algorithms. It’s a tougher balancing act now.”
Users of the 10nm process expect to be able to take advantage of the higher electrical performance of the finFET to reduce supply voltages as close as possible to the threshold voltage. At the same time to maximize their return on investment, chipmakers want to push performance as much as possible and so reduce the amount of timing margin they apply to deal with variability problems.
“The core transistors are faster and timing violations have been reduced to a matter of picoseconds. Variability increases as the voltage reduces, and the libraries being developed for 10nm are going to very low voltages. To avoid excessive margining, timing analysis needs to be more accurate. One way to address this is through the use of techniques such as statistical OCV,” Smith says.
The core of the Cadence flow for 10nm is the Innovus Implementation System, which deploys massive parallelism to enable the increased capacity required and a reduced turnaround time. As well as support for place-and-route with awareness of mask color, cell pin-accessibility, and variability, the system provides clock tree and power optimizations for 10nm processes, such as TSMC’s.
The implementation flow is supported by the Quantus QRC Extraction Solution, which supports both cell-level and transistor-level extractions during design implementation and signoff. It meets TSMC accuracy requirements for all 10nm modeling features, including multipatterning, multicoloring, and 3D extraction capability. Because of the high density of 10nm designs, Cadence put emphasis on producing netlists as small as possible to keep simulation runtimes down.
Also in the flow are the Tempus Timing Signoff Solution for full statistical OCV-based timing analysis and the Voltus IC Power Integrity Solution, which performs comprehensive checks against electromigration and IR-drop (EM/IR) design rules and requirements for the TSMC 10nm process.
Work continues on the 10nm flow as the process nears maturity to take advantage of new optimizations to ensure high PPA.