May 12, 2017
Among the papers at this year's VLSI Symposia in Hawaii in June, Samsung will describe a 7nm CMOS process that uses EUV lithography to tighten up device features on minimum-pitch interconnects.
October 24, 2016
At the 62nd annual IEDM taking place in early December two of the leading groups in process development will take the wraps off their 7nm finFET technologies.
February 23, 2016
Directed self assembly techniques may offer similar benefits to EUV lithography, especially for DRAM makers, says SPIE conference paper
February 11, 2016
The Calibre vendor will have a strong technical presence at the leading lithography conference taking place in late February in San Jose.
October 9, 2015
IMEC and Cadence have taped out a test chip intended to explore key lithography and metal-interconnect issues that will face users of the forthcoming 5nm process node.
July 9, 2015
IBM, GlobalFoundries, Samsung and SUNY deserve kudos for manufacturing the first 7nm chip but the NREs involved still look frightening.
September 11, 2014
EUV may be getting most R&D cash but the world's biggest foundry says e-beam currently has the edge on defects and double patterning.
June 13, 2014
Panel discusses Moore's law scaling beyond the 14nm node to 5nm, where economic, device, interconnect, materials, lithography and design issues abound
March 26, 2014
IMEC's Rudy Lauwereins explained at DATE 2014 how 1D routing for self-aligned multiple patterning is likely to be inevitable even if EUV makes it into production fabs.
May 22, 2013
Plan around 193nm immersion lithography. Alternatives are years off and not guaranteed, says analyst group