Siemens has launched Calibre DRC engines that make it easier to perform useful checks early in the layout process.
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
IP and EDA vendors line up to support TSMC 20nm process, CoWoS 3DIC technology
Guest blogger Jeff Wilson discusses some of the subtleties involved in the effective use of dummy fill in deep sub-micron IC designs.
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