TSMC certifies Synopsys tool flow for 7nm EUV process
TSMC has certified a tool flow from Synopsys for use on its 7nm FinFET Plus process, which includes steps that demand EUV lithography. The tool flow also supports multi-die integration using TSMC’s Wafer-on-Wafer (WoW) packaging technology. The flow has already been used for test chips, and production designs are underway.
The Synopsys Design Platform includes Design Compiler Graphical synthesis, and IC Compiler II place-and-route tools. Design Compiler Graphical can automatically insert via pillars to address performance and electro-migration issues on signal paths, and can pass information about their use to IC Compiler II for further optimization. DC Graphical can also apply non-default rules during synthesis and perform layer-aware optimizations to improve performance. IC Compiler II offers bus-routing features that help meet the stringent delay-matching requirements of high-speed networks.
PrimeTime has been updated with advanced waveform propagation and parametric on-chip variation technologies to address increased waveform distortion and non-Gaussian variation effects of higher-performance processes operating at lower voltages. PrimeTime’s physically aware sign-off has also been extended to support the use of via pillars.
The Synopsys Design Platform has also been updated to perform physical implementation, parasitic extraction, physical verification, and timing analysis on designs that use TSMC’s wafer stacking process. IC Compiler II’s physical implementation flow covers WoW design issues such as preparing an initial die floorplan, the placement and assignment of bumps, and die routing. IC Validator can be used for DRC/LVS checks, and StarRC can be used to perform parasitic extraction on such designs.
Suk Lee, senior director of the design infrastructure marketing division at TSMC, said in a statement: “Certification of the Synopsys Design Platform enables our mutual customers’ designs in our first mass-production, EUV-enabled technology.”
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