Synopsys takes TSMC design into the cloud; IP to 7nm, 5nm and automotive processes

By TDF Staff |  No Comments  |  Posted: October 9, 2018
Topics/Categories: Design to Silicon, Blog - EDA, IP, - Verification  |  Tags: , ,  | Organizations: , ,

Synopsys is taking IC design on TSMC processes into the cloud with the launch of the Synopsys Cloud Solution, which will run on platforms from Synopsys, Amazon Web Services or Microsoft Azure.

The Synopsys Cloud Solution will enable SoC designers to run design and verification tasks on cloud infrastructure using Synopsys EDA tools and IP, IP from Arm, and TSMC collateral, including process technology files, process design kits (PDKs), and foundation IP.

The Synopsys Cloud Solution offers access to Synopsys design and verification platforms, reference flows, and a load-based license server. Synopsys’ Lynx Design System design management tool provides automation and enables designers to take advantage of the massive scaling possible with tools including PrimeTime signoff; StarRC extraction; IC Validator signoff physical verification; HSPICE, CustomSim, and FineSim circuit simulation; SiliconSmart characterization; VCS functional verification; VC Formal formal verification; and Z01Xfault simulation.

Synopsys’ IP group has already used the cloud offering to tape out a high-speed DesignWare PHY IP block for PCI Express 5.0 on TSMC’s 7nm process quickly, by running the IC Validator signoff physical-verification tool on thousands of CPU cores.

Arm has worked with Synopsys to offer cloud-proven QuickStart Implementation Kits for its processor cores, including the recently announced Cortex-A76, in a form appropriate to the process.

The Cloud Solution offering is one of a series of recent announcements involving the two companies.

Synopsys is also developing DesignWare interface IP, logic libraries and embedded memories for TSMC’s N7+ FinFET process. Some of these IP blocks have already been taped out in multiple customer designs on the process.

The logic libraries, embedded memories, and PHYs supporting USB 2.0/3.1, DisplayPort, PCI Express 3.1, and MIPI M-PHY are available now in the N7+ process, as are the STAR Memory System and STAR Hierarchical System tools. DesignWare IP blocks for DDR, LPDDR, MIPI D-PHY, PCI Express 4.0/5.0, 25G Ethernet, and SD/eMMC should be available on the process in the first half of next year.

Synopsys has also delivered automotive-grade DesignWare controller and PHY IP for TSMC’s 7nm FinFET process. The DesignWare LPDDR4x, MIPI CSI-2 and D-PHY, PCI Express 4.0, and security IP blocks are implemented using automotive versions of the standard design rules to meet the stringent reliability and operation requirements of automotive SoCs.

The IP meets stringent AEC-Q100 temperature requirements, delivering high reliability for automotive SoCs, and is delivered with the Failure Modes, Effects, and Diagnostic Analysis reports required to meet automotive functional-safety requirements.

TSMC has also just certified Synopsys’ digital and custom design platforms on TSMC’s 5nm, EUV-based process technology. The certification is the result of a multi-year partnership to deliver an optimized design solution for this advanced process node.

The Design Compiler Graphical synthesis tool has been validated on the process and has shown timing, area, power, and congestion resuls that are correlated with the output of the IC Compiler II place-and-route tool suite. Optimizations for the 5nm process include better via-pillar optimization, multibit banking, and pin-access optimization.

The tool has also been adjusted to handle complex, multi-variant and two-dimensional cell placement natively during optimization, while maximizing routability and overall design convergence.

PrimeTime’s parametric on-chip variation analysis capabilities have been updated to better reflect greater non-linear variation due to process scaling and low-voltage operation. The tool’s physically aware ECO facilities have been strengthened to support more complex layout rules for better congestion, placement, and pin-access awareness.

Synopsys Design Platform technology files, libraries, and parasitic data are available from TSMC for the 5nm technology process.

Finally, Synopsys’ Design Platform has been upgraded to handle TSMC’s wafer-on-wafer (WoW) direct stacking and chip-on-wafer-on-substrate (CoWoS) packaging technologies. The solution now includes multi-die and interposer layout implementation as well as parasitic extraction and timing analysis, coupled with physical verification. A reference flow will enable early customers to explore the 3DIC packaging technologies for high-performance and low-power applications.

The platform-wide Synopsys solution includes multi-die and interposer layout capture, physical floorplanning, and implementation, as well as parasitic extraction and timing analysis coupled with physical verification.

Reflecting the closeness of the relationship between TSMC and Synopsys that has enabled thse announcements, TSMC last week recognized Synopsys with four partner awards at it Open Innovation Platform Forum event.

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