Cadence and Imec tape out 3nm interconnect test chip

Cadence Design Systems and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.

The joint test-chip project follows on from an earlier “pipe cleaner” test chip that used more basic structures to evaluate the effects of 3nm lithography rules. In addition to test structures that will be used to determine the performance of interconnect layers with a minimum 21nm pitch, the test chip design incorporates layout features derived from a 64bit processor core created using Cadence’s synthesis and place-and-route tools.

Peter Debacker, R&D team leader at Imec, said: “The design flow was based on a full PDK but this test vehicle is aimed at back-end-of line (BEOL) analysis. It takes various layers of the design, from the last middle-end-of-line (MEOL) layer up to BEOL metal.”

The standard-cell library created by Imec for the project assumes the use of finFETs at 3nm but Debacker said only minor modifications would be needed in the interconnect layers modeled to support lateral nanowires, which may be needed instead of finFETs at that node. “This is our first view of what a 3nm standard cell architecture would look like and how those cells would be integrable,” he added. “We selected the most likely process options and chose various design rules to allow comparison of the effects of patterning.”

One of the aims was to investigate the effect on design and manufacturing choices over track height and standard-cell geometry would have on the forthcoming process. “We are trying to push track height to as low as it will go. We are trying to do better than the six track that’s out there in the current process nodes,” Debacker said. “We got valuable feedback from Cadence. If we propose a cell architecture, no matter how crazy it looks, it has to work for the EDA tools. It’s an ongoing cooperation. We could scale features by 50 per cent but if we didn’t think about the effect on routing we might only end up with 25 per cent scaling. The changes need to achieve better scaling might be in the EDA tools or there might be a fundamental [manufacturing] limit.”

Lithography mix

For the layout of the interconnect, Imec and Cadence assumed a mixture of EUV and 193nm immersion with both lithography technologies using self-aligned spacer patterning supplemented by cut masks. “At a 21nm pitch, it’s not possible to EUV single patterning,” Debacker said.

Using EUV and immersion-based design rules, Imec expects to be able to demonstrate the impact on design and yield for each so that customers can then decide how best to split the lithography across different interconnect layers.

“We will use this test vehicle to run different process options, explore different resist options and also look at the metal fill,” Debacker said, noting that the processor-based structures would help show up problems caused by different densities of interconnect across an area equivalent to a full core. “Place-and-routed blocks are where everything comes together. A block like this stresses the design rules in ways you might not have foreseen [with standard test-chip structures].”

Rod Metcalfe, director of Cadence’s implementation group, said: “This type of project is very useful from an EDA standpoint. Imec creates standard-cell libraries from which we can learn how best pin-access can work. It’s very early in the discussion as to how 3nm will work but Imec can come to us with ideas: ‘If we did this, how would it work in the EDA tools?’ We can determine if the router, for example, needs to understand more things.”

Metcalfe said the test chip also provides the opportunity to see how power grids can best align with the signal routing. “The power structures have a big impact on the EDA side. They can affect the placement significantly and it is a surprisingly important part of the work we’ve done with Imec. One of the valuable things we can learn is how the placer reacts to these things.”