Flow evolution for the 3DIC/chiplet age

By TDF Editor |  No Comments  |  Posted: October 24, 2023
Topics/Categories: Blog - EDA, - General, Packaging, Physical design, Verification  |  Tags: , , , , , , , ,  | Organizations:

The increasing use of 3DIC and, within that, chiplet strategies has already brought forward a number of key ‘known unknowns’ as design challenges. A new White Paper discusses the main concerns and how design flows and tools are evolving to meet them.

Some of the main problems that traditional IC tools do not address revolve around how these types of design evolve – identifying which third party chiplets to include is a leading challenge for exploration.

Beyond that, there are the issues vertical chiplet stacking present to automated routers – in particular, they cannot be handled as uniform shapes for a layer map.

“Traditional physical verification tools look at design data from a two-dimensional (2D) perspective. While there can be an implied vertical differentiation between layers, overlapping or abutting geometries on the same layer are considered as if they represent a single shape,” explains author John Ferguson of Siemens Digital Industries Software.

“In 3DIC design, chiplet designers cannot rely on this 2D approach, because they simply don’t know what may be vertically stacked in the 3DIC design. Geometries on a layer in one chiplet that happen to overlap with geometries in another chiplet vertically placed above or below it cannot and should not be considered as a single shape.”

A further chiplet challenge is represented by the heterogeneous sourcing of chiplets, possibly in different processes and manufactured within the constraints of multiple foundry PDKs.

Then there are new concerns related to thermal and mechanical stress, less of a problem for traditional ICs but which require more detailed analysis for chiplets around power, electromigration and IR drop.

Ferguson describes how these factors are now being addressed within a combination of EDA tools including those that address areas including physical verification (notably Calbre 3DSTACK and PERC), prototyping and design exploration (Xpedition Substrate Integrator – xSI), layout (Aprisa) and packaging (Xpedition Package Designer – xPD).

Successful 3DIC design, verification, and analysis requires an integrated approach is available‘ is available for download at this link.


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