Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
Siemens introduces mPower to bridge the analog-to-digital gap in IR-drop and EM analysis, reflecting the scaling trends in today's ICs.
Cadence Design Systems has made enhancements to its Virtuoso mixed-signal layout tool at both the system-level and nanometer-design levels for its 18.1 release.
DesignCon 2017 takes place from Jan 31 to Feb 2 at the Santa Clara Convention Center with its usual focus on PCB design and implementation.
Award-winning paper describes new strategy offering both greater speed and accuracy.
Ansys has decided to marry cloud computing with some of the tools used in SoC design that can make use of large amounts of temporary computer power.
Mentor Graphics has launched Calibre xACT, a tool that uses deterministic algorithms to extract parasitics from complex finFET and other nanometer processes.
Cadence Design Systems has introduced a variant of Voltus that runs transistor-level simulations to check for electromigration and IR-drop problems.
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