Nvidia open to chiplet standards
Nvidia plans to adopt a standard for chiplet interfaces being developed by a collective of packaging and semiconductor companies as soon as it becomes “stabilized” but will focus on it as a way of connecting peripherals, with its own NVLink-C2C being promoted as a processor-processor interconnect.
The GPU maker revealed its plans for the Universal Chiplet Interconnect Express (UCIe), which turns the existing PCIe interface into a chiplet interconnect specification, at the company’s GTC Spring conference this week (March 21st). Though the UCIe consortium said it had published its version 1.0 specification at the beginning of the month, Nvidia co-founder and CEO Jensen Huang said in a Q&A with journalists during GTC, “UCIe is still being developed. And it’s a recognition that in the future you want to do system integration not just at the PCB level but have the ability to integrate even at the multichip level with another [from of] PCIe: UCIe is a peripheral bus.
“I’m a big believer in UCIe just as I’m a big believer in PCIe. It has to become a standard so I could take a chip from Broadcom, Marvell, TI, or Analog Devices and just connect it to my chip. I would love that and that day will come. But it will take, as it did with PCI Express, about half a decade. As soon as the UCIe spec is stabilized we’ll put it into our chips as fast as we can,” Huang added.
At the same conference, Nvidia said it is opening up its latest form of NVLink to other suppliers so they can connect processors and accelerators that need a cache-coherent interface to host processors. The NVLink-C2C interface uses the same interconnect as that planned for the Grace multichip modules that Nvidia expects to ship next year and which supports Arm’s Amba Coherent Hub interface (CHI) protocol as well as CXL. The company said it is working with Arm to be able to support fully coherent operation with devices that support security protections.
The company claimed NVLink-C2C can be 25 times more energy efficient and 90 times more area-efficient that PCIe Gen 5 as a chiplet interconnect.
“NVLink is now in its fourth generation. We’ve been working on these high-speed chip-to-chip links now for coming up on eight years. We ship more NVLink or chip-to-chip interconnect than just about anybody. And we believe in this level of integration,” Huang claimed. “It’s one of the reasons why Moore’s Law stopping never stopped us. We just kept on building larger and larger systems, and it was all made possible by NVLink.
”In the future, there’ll be little tiny things that you can connect directly into our chip. As a result, a customer could do a semicustom chip with just a little engineering effort and connect it into ours and differentiate it in their own data center in their own special way. Nobody wants to spend $100bn or $100m to differentiate, they would love to spend $10 million to differentiate, leveraging off of somebody else’s 100 million. You are going to bring a lot of those kinds of exciting opportunities,” Huang concluded.
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