3nm


October 22, 2018

IEDM to examine scaling from multiple directions

CMOS moving to 3nm and DRAM going beyond 20nm scaling are two of the late papers at the upcoming IEDM and part of a larger examination of semiconductor trends.
Article  |  Topics: Blog - EDA, IP  |  Tags: , , , ,   |  Organizations: , ,
June 22, 2018

Imec stacks transistors for denser 3nm option

Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
Article  |  Topics: Blog Topics  |  Tags: , , , , ,   |  Organizations:
February 28, 2018

Cadence and Imec tape out 3nm interconnect test chip

Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
February 16, 2018

SPIE Advanced Lithography 2018 preview: Mentor

Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
Article  |  Topics: Conferences, Design to Silicon  |  Tags: , , , , , , ,   |  Organizations: ,
June 20, 2016

DTCO points to sub-10nm optimizations

DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.
Article  |  Topics: Blog - EDA, Embedded  |  Tags: , , , , , ,   |  Organizations: ,

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