IEDM homes in on connected devices

By Chris Edwards |  No Comments  |  Posted: September 4, 2019
Topics/Categories: Blog - EDA  |  Tags: , , ,

The upcoming 65th annual IEEE International Electron Devices Meeting (IEDM) has taken on the theme of “Innovative Devices for an Era of Connected Intelligence.”

Taking place December 7-11, 2019 at the Hilton San Francisco Union Square hotel, the”>conference will as before feature the latest important research into semiconductors and other electron devices. But it will have a sharper focus this year on devices intended to support the diverse applications of connected devices, though it will also delve into quantum computing concepts.

Quantum computing is among the focus session topics that will be featured at IEDM, alongside AI technologies; human-machine interface devices; and reliability for circuits and systems.

“IEDM 2019 will feature state-of-the-art results from major semiconductor companies, universities and other research institutions around the globe, continuing the conference’s tradition of being the premier venue for the presentation of the highest quality research,” said Rihito Kuroda, IEDM 2019 publicity chair and associate professor at Tohoku University. “While CMOS scaling remains very important and IEDM once again will feature the latest work in that area, many diverse new, fast-growing applications demand different types of devices. Therefore, we have reorganized the technical subcommittee structure of IEDM to better align the conference with the innovative semiconductor concepts and technologies required.”

In addition to a full conference of technical papers, 90-minute tutorials will take place on Saturday, December 7. These cover topics such as oxide semiconductors and thin-film transistors; ferroelectric memories; in-memory computing for AI; magnetic sensors; and 3D monolithic integration.

The organizers recommend early registration for the following full-day Sunday short courses is recommended because they are often sold-out. They offer the opportunity to learn about technology scaling in the EUV era and beyond; logic transistor options and advanced processes for the 3nm node and beyond; design technology co-optimization; novel interconnect techniques for CMOS; and technologies for memory-centric computing.

As with earlier years, a vendor exhibition will be held as part o the conference in addition to two two poster sessions: one on MRAM technology organized by the IEEE Magnetics Society; the other a student research showcase hosted by the Semiconductor Research Corporation.

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