TSMC fills in sub-nodes as EUV gains ground
TSMC is using its growing experience with EUV lithography to fill in sub-nodes between its major releases as it prepares to extend finFET technology to the forthcoming N3 process rather than opting for nanosheet or some other gate-all-around device shape.
Following on from the introduction of the N5P node due to ramp in 2021, on which NXP Semiconductors aims to build automotive navigation SoCs, TSMC aims to produce a node it calls N4 that will arrive in risk production towards the end of next year.
“We are now deriving N4 from N5 to cover a wider range of product needs,” said TSMC CEO CC Wei at the start of the company’s annual OIP symposium, held entirely online for the first time. “It will offer IP compatibility with N5 so you will be able to leverage the fully fledge design infrastructure that is in place.”
N4 uses more EUV layers to reduce the number of mask layers, said YJ Mii, senior Vice President of R&D at TSMC. “The migration from N5 to N4 is fairly straightforward. It has compatible design rules, SPICE models and IPs.”
N7 successor cuts layers
At the same time, TSMC is bringing in an N6 sub-node that also incorporates more EUV-defined layers to improve on the N7 density by 18 per cent. Mii said the lower process complexity is expected to lead to better yield on N6 than on N7. Senior vice president of R&D Cliff Hou said customers have the option to use N6-specific cell libraries and resynthesize to gain area savings while reusing existing N7 hard macros or to simply transfer an N7 design to N6 and gain yield improvements from the lower mask count.
“Scaling continues through EUV breakthroughs and improvements in OPC, materials, resists, multi-patterning and so on,” Mii claimed. One of the results of R&D so far is a self-aligned spacer combined with EUV lithography to yield an interconnect pitch of 18nm. “This will allow further interconnect scaling and, with DTCO, will deliver further PPA benefits.”
Wei said N3 itself will offer a 70 per cent density improvement over N5, with 15 per cent higher clock speeds at the same power or 30 per cent lower power at the same clock. Analog circuit density will be about 10 per cent higher. Volume production for this is currently slated for the second half of 2022, after N4 has ramped to production.
“After carefully evaluating customer needs, N3 continues to use a finFET device structure. We believe it will be the most suitable choice for customers,” said Mii. “Our goal is to provide the right technology at the right time.”
Wei said the foundry is talking to customers about the future direction beyond N3 and the type of device it will offer. Mii added the company has “made significant progress in nanosheet and nanowire, and made major breakthroughs in new materials”. He pointed to reseach disclosed at recent IEDM and VLSI Symposia conferences where nanosheets were used in a 32Mbit SRAM test vehicle and results on drain-induced barrier lowering using the GAA structure. He also talked about work on 2D materials such as molybdenum disulfide and tungsten diselenide as possible alternatives to mobility-enhanced silicon in nanosheet-type transistors.
FinFETs also form the core of a process being introduced for IoT and low-power edge computing that is intended as a follow-on from the 22nm ULL process. N12e is based on 12FFC+ and is intended to offer a density improvement of 75 per cent and less than half the power consumption of its predecessor. Hou said the foundry has worked out a revised flow for customers to check designs given the lower headroom in terms of variability when taking advantage of lower supply voltages.
For 3DIC production, TSMC has decided to bring its three main approaches to system-in-package (SIP) production under one umbrella, called 3DFabric “to better organise the portfolio”, said Doug Yu, vice president of R&D for integrated interconnect and packaging.
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