June 22, 2018
Imec proposes using stacked CMOS transistors and buried power rails to improve density for the 3nm process node.
February 28, 2018
Cadence and Imec have worked together on a project to tape out a test chip to explore manufacturing and design-rule options for the interconnect on future 3nm processes.
February 16, 2018
Innovation and advances in EUV and OPC lead Mentor's offerings at SPIE in San Jose later this month.
June 20, 2016
DTCO work by GlobalFoundries and Qualcomm reported at VLSI Symposia shows the need to minimize fin counts in future finFET processes.