EDA

February 26, 2020

DVCon US 2020 preview: ESD Alliance

The Electronic System Design Alliance will discuss the benefits it offers for design and verification, and has added Avery Design Systems.
Article  |  Tags:   |  Organizations: , , ,
February 26, 2020

DVCon US 2020 preview: Verific

Tool development specialist Verific will demonstrate its parsers and their integration with INVIO APIs.
Article  |  Tags: , , , , ,   |  Organizations: ,
February 24, 2020

DVCon US 2020 preview: Mentor

Mentor will have a very broad presence at DVCon across technologies such as HLS, formal verification, simulation and emulation.
Article  |  Tags:   |  Organizations: ,
February 18, 2020

Accellera moves to working-group stage for functional-safety standard

Accellera has set up a working group with the aim of developing interoperability standards for functional safety.
Article  |  Tags: , ,   |  Organizations:
January 28, 2020

Earlier latch-up prevention with topology-based analysis

By analyzing topology during the schematic design phase, you can detect latch-up issues before post-layout ERCs and avoid late stage revisions.
January 19, 2020

Verific celebrates two decades of parser pre-eminence

The parser specialist has built a loyal fanbase across the electronics system design infrastructure with users now lining up to mark its 20th birthday.
Article  |  Tags: ,   |  Organizations: , , , , ,
January 7, 2020

Siemens and Arm combine to extend digital twin further into SoC design

Partnership combines Siemens PAVE 360 digital twin with ARM IP, including dedicated automotive offerings, to speed and streamline design toward Level 5.
Article  |  Tags: , , , ,   |  Organizations: , ,
December 18, 2019

On-demand DRC within P&R cuts closure time in half for MaxLinear

Case study describes how RF/AMS specialist used Calibre RealTime Digital within its flow for a high-end DSP SoC.
December 18, 2019

Capacitive link to power cheap wireless tags

Imec, TNO, and Cartamundi have developed a low-cost way of letting tags communicate with embedded devices wirelessly by using a capacitive touchscreen.
Article  |  Tags: , ,   |  Organizations:
December 17, 2019

Automating the pain out of clock domain crossing verification

A new CDC methodology uses automation and data hooks to improve a notoriously lengthy and tricky task - verifying synchronizers.
Article  |  Tags: , , , ,   |  Organizations: ,

PLATINUM SPONSORS

Synopsys Cadence Design Systems Mentor - A Siemens Business
View All Sponsors