Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
Three EDA vendors team up to create stronger verification flow for RISC-V processor implementations.
Siemens has launched Calibre DRC engines that make it easier to perform useful checks early in the layout process.
Cadence president expects expanded role for reinforcement learning in tool portfolio and looks for help on AI for verification.
Siemens EDA has launched a second version of its Symphony simulation environment designed to support quicker debug cycles.
Agile Analog's oscillator IP sees the company focus on IP created with its own circuit creation and porting tool.
Aki Fujimura of mask specialist D2S sees curved shapes as key to improving die yield and performance but it needs EDA support.
Optima DA has turned its high-throughput fault-simulation technology to the checking protections against aggressive, intrusive hacks.
The ESD Alliance is hosting a panel and networking event at next week's colocated Design Automation Conference and SEMICON West.
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