September 27, 2022
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
September 15, 2022
Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
September 14, 2022
X-Fab is using IHP technology to add a 130nm silicon germanium process to its offering.
September 8, 2022
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
September 8, 2022
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
September 5, 2022
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
September 5, 2022
Learn how one of the leading tool vendors addresses the security of its products and customer data through a ground-up cybersecurity strategy.
August 31, 2022
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
August 3, 2022
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
August 3, 2022
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.