Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
Real Intent has developed a tool to check design and the potential for circuits to glitch.
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
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