EDA

April 4, 2023

Curvilinear layout looks to wider adoption with mask speedups

Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
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March 30, 2023

SEMI predicts strong 300mm growth to 2026

SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
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February 28, 2023

Imperas and Synopsys team on RISC-V debug

Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
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January 18, 2023

Accellera forms CDC working group and takes security standard to IEEE

Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
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January 6, 2023

DVCon Europe best paper speeds up memory-controller tests

The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
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January 4, 2023

A*Star lays out SiP applications choices at IEDM

The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
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December 9, 2022

Imec adds MOL layer to potentially cut cell size 20%

Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
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November 21, 2022

DVCon Europe looks to network effects

Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
November 15, 2022

Real Intent tool looks for glitches

Real Intent has developed a tool to check design and the potential for circuits to glitch.
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November 14, 2022

Semiwise brings cryogenic models to SOI

Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
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