April 4, 2023
Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
March 30, 2023
SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
February 28, 2023
Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
January 18, 2023
Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
January 6, 2023
The winner of the best-paper award at DVCon Europe went to a team from Samsung based in India, describing their work on a reusable agent for testing the behavior of error-correcting memory circuits.
January 4, 2023
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
December 9, 2022
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
November 21, 2022
Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
November 15, 2022
Real Intent has developed a tool to check design and the potential for circuits to glitch.
November 14, 2022
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.