EDA

Tessent RTL Pro allows wrapper cells and x-bounding logic to be inserted earlier in designs.

MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.

Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.

Siemens and CEA-List have signed a deal under which the two organisations will research the combination of digital-twin and AI.

DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.

Accellera has formed a working group to look at the possibility of creating a standard for federated simulation.

Just how much of the flow has already has 'shift left' benefit and what is fueling further progress.

Tessolve is bringing its Verification Futures conference to the US with an event scheduled for mid-September.

Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.

The recent Verification Futures Europe conference looked at what AI, from decision trees to foundation models, could do to speed up RTL checks.