Mentor, a Siemens business, has rebranded as Siemens EDA, almost almost four years after the EDA company was acquired.
Aldec updates tools to add support for the latest release of the VHDL verification methodology.
Less than one-in-five FPGA projects avoid bug escapes (Wilson Functional Verification 2020 – Part Two)
Benchmark study detects correlation between maturity of verification processes and the quality of designs when they reach production.
Accellera Systems Initiative has published for open review version 2.0 of the Portable Test and Stimulus standard.
This year's IEDM will feature papers that exploit stacked nanoribbons to reduce CMOS footprint, graphene interconnects that support easier integration, and the variability prospects of 2D semiconductors.
The free-to-attend user meetings for Mentor clients will retain the same format mixing technical presentations with keynotes and networking.
Speakers at this year's DVCon Europe called on the hardware community to find inspiration in software-development trends.
Functional verification for increasingly complex ARM-based designs is at the heart of the new consultancy partnership.
Among the papers that will be presented at the end of October, this year's DVCon Europe will demonstrate the benefits of taking good ideas from wherever you can in the pursuit of more effective verification flows.
As part of its move online during the pandemic, DVCon Europe is introducing what the organizers call Virtual Experience Rooms.
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