EDA

November 14, 2023

Imec makes virtual fab public for green analysis

Imec has a version of its imec.netzero virtual fab tool accessible to the general public with the aim of showing the environmental impact of IC manufacturing.
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November 6, 2023

Cadence combines ML techniques for power signoff

Cadence has linked several machine-learning approaches to build a tool that is designed to speed up the detection and diagnosis of on-chip power-integrity issues.
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October 31, 2023

Accellera publishes draft of CDC standard

Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
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October 25, 2023

Image sensors shrink at IEDM

This year’s IEDM features a number of papers that seek to drive down the size and boost the performance of image sensors.
October 25, 2023

VLSI Symposium 2024 looks to bridge digital and physical

The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.
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October 24, 2023

Flow evolution for the 3DIC/chiplet age

Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
October 16, 2023

Accellera updates portable stimulus standard

Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
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October 9, 2023

ITC 2023 preview: Siemens DIS

From tutorials to technical papers to special 'diamond' sessions, Tessent features large at ITC 2023.
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October 9, 2023

Tessent speeds ‘shift left’ drive for test at RTL

Tessent RTL Pro allows wrapper cells and x-bounding logic to be inserted earlier in designs.
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October 6, 2023

Fast instruction simulator expands to Arm

MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.

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