June 21, 2021
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
June 17, 2021
A de facto standard for exchanging thermal information about designs has become JEDEC standard JEP181.
June 16, 2021
Samsung described at VLSI Symposia how it has used two further forms of stacking to increase flash capacity.
June 15, 2021
Imec showed at VLSI Symposia a process flow that can cut the gap between complementary transistors to less than 20nm.
June 14, 2021
At the VLSI Symposia, researchers described how AI hardware could help dramatically accelerate analog and digital design and not all of it directly through machine learning.
June 4, 2021
IEDM has issued a call for papers for what the organizers expect to be an in-person event in December.
June 3, 2021
TSMC will provide three different standard-cell libraries for its upcoming finFET-based 3nm process to cover requirements from high-density mobile to high-performance computing, allowing tradeoffs for area and circuit frequency.
May 28, 2021
Questa suite of VIP adds PC and enterprise protocol as players prep designs for 2023 release.
May 21, 2021
Cadence has launched a reworked FastSpice engine designed to split work across multiple cores more efficiently.
May 13, 2021
Sigasi aims to attract developers working on open-source projects with a version of its Studio suite the company is making available for free to that community.