A DVCon technical paper addresses potential reset domain crossing metastability issues due to UPF instrumentation.
DVCon Europe has announced its first two keynote speakers, who will cover the topics of AI and the role of virtualisation in ADAS design and implementation
DAC and the RISC-V Summit will colocate at Moscone West in December, along with Semicon West.
A Siemens white paper describes a way of automatically deriving information from 2.5D/3DIC designs to streamline latchup design-rules verification.
STMicroelectronics has made its first silicon carbide wafers that can be run on a 200mm line.
Cadence has launched a tool that the company claims can speed up implementation by applying machine learning across the flow.
Arm and flexible-electronics specialist PragmatIC have demonstrated a 32bit processor implemented on a plastic substrate.
Building products using chiplets involves more than treating them as hard IP cores. Many open questions surround the field, explored by panelists in a MEPTEC conference online.
The added complexity of managing reliability as chiplet-based designs become more common will need to be managed using digital-twin techniques, says a professor working in the field.
Learn how Calibre RealTime Digital allows you to identify, explore and fix DRC violations as you go.
View All Sponsors