EDA

July 20, 2020

Mentor tunes LVS for early SoC integration

Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
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July 20, 2020

Verifyter offers regression analysis for six months free

At DAC this week, Verifyter is offering a limited number of companies free six-month licences of its regression-analysis tool Pindown.
July 13, 2020

Heterogeneous integration calls for new approaches

Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
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July 8, 2020

Scaling costs tip balance toward chiplets for AMD server processors

In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
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July 7, 2020

DVCon Europe goes virtual

The organizers of DVCon Europe have decided to turn the autumn verification conference into a virtual event this year.
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July 1, 2020

Sigasi creates SDK for custom editors

Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.
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June 24, 2020

IEDM switches to virtual format for 2020

The organizers of the 66th annual IEDM have decided to hold the December conference virtually.
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June 18, 2020

Kioxia looks to waferscale flash drives for fast, low-cost storage

Waferscale SSDs are among the future drive architectures being explored by Kioxia, according to a keynote delivered at VLSI Symposia.
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June 18, 2020

How Ambarella met the demands of automotive DFT

Even experienced IC design houses must adopt innovative and emerging strategies to meet functional safety and other demands of ISO 26262 for automotive systems.
June 16, 2020

Transistor stacks piled high at VLSI

As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.

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