EDA

May 23, 2022

IEDM to celebrate 75 years of the transistor

Recognizing the 75th anniversary of the transistor in December, the 68th IEDM has taken on the theme of looking at “transformative devices to address global challenges”.
Article  |  Tags: , , , ,   |  Organizations: ,
May 12, 2022

Extended coverage for sign-off analysis

Real Intent has extended the fault coverage of its Meridian DFT static sign-off tool with improvements to the reporting of issues and the ability to track down root causes.
Article  |  Tags: , ,   |  Organizations:
May 5, 2022

DAC returns to SF for in-person event

DAC returns to San Francisco in July for its 59th year as a purely in-person event.
Article  |  Tags: , , ,   |  Organizations:
April 28, 2022

DVCon Europe returns to live format

DVCon Europe will be held as a live event in Munich in early December.
Article  |  Tags: ,   |  Organizations:
April 27, 2022

Verifying the new namespace storage options in NVMe 2.0

The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Article  |  Tags: , , , ,   |  Organizations:
March 23, 2022

Nvidia open to chiplet standards

Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
Article  |  Tags: , , , , ,   |  Organizations:
March 4, 2022

Verification engineers look to better skills to beat schedules

A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Article  |  Tags: , , , , , ,   |  Organizations: , , ,
March 2, 2022

Synopsys talks AI in verification at DVCon

Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
Article  |  Tags: , , , ,   |  Organizations:
February 8, 2022

How digital twin evaluations optimize STCO-based design

System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
January 25, 2022

Choose the right advanced packaging methodology for metal fill rules

Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.

PLATINUM SPONSORS

Synopsys Cadence Design Systems Siemens EDA
View All Sponsors