EDA

Calibre Design Enhancer moves physical verification checks and automated DRC-clean via and cell insertion into P&R

Three fast developing AI techniques underpin the efficiencies in the new Solido custom design and verification platform.

At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.

Siemens has published a white paper that examines whether package designers need to adopt IC tools and design styles in the move from organic packages to 2.5DIC packages.

A comprehensive review of ML's potential and its current use identifies challenges ahead.

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.

DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.

Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.

SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.