Mentor has released a tool that attempts to deal with the problems encountered in the use of physical circuit verification in the early stages of SoC integration.
At DAC this week, Verifyter is offering a limited number of companies free six-month licences of its regression-analysis tool Pindown.
Heterogeneous integration has the potential to overcome the yield and cost challenges presented by the growing headwinds associated with process scaling. But it may take a dramatic rethink in design approaches.
In a panel session at VLSI Symposia, AMD described how the economics have come down strongly in favor of multichip integration for multicore server processors.
The organizers of DVCon Europe have decided to turn the autumn verification conference into a virtual event this year.
Sigasi has launched a software kit to provide inhouse tools builders and EDA vendors with a way to build in code-editing features.
The organizers of the 66th annual IEDM have decided to hold the December conference virtually.
Waferscale SSDs are among the future drive architectures being explored by Kioxia, according to a keynote delivered at VLSI Symposia.
Even experienced IC design houses must adopt innovative and emerging strategies to meet functional safety and other demands of ISO 26262 for automotive systems.
As 2D scaling becomes increasingly difficult, researchers reporting at VLSI Symposia have focused attention on what can be done in the third dimensions to improve density and performance without a sudden break from conventional CMOS processes.
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