EDA

July 4, 2023

Co-design underpins infrastructure acceleration at Google

At the recent VLSI Symposium, Google vice president Parthasarathy Ranganathan described the importance of co-design and the software stack in its data-center designs.
June 1, 2023

Does 2.5DIC call for IC design tools for the packaging?

Siemens has published a white paper that examines whether package designers need to adopt IC tools and design styles in the move from organic packages to 2.5DIC packages.
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May 30, 2023

Charting the path for machine learning in functional verification

A comprehensive review of ML's potential and its current use identifies challenges ahead.
April 25, 2023

Alps Alpine composes capacitance IC with Symphony

The company says the mixed-signal platform enabled a 5X improvement in verification productivity.
April 17, 2023

Achieving functional coverage of multi-language designs

There is no comprehensive standard yet for functional coverage across designs using SystemC, TLM, UVM and SystemVerilog, but there are options using UVM Connect.
April 17, 2023

DVCon Europe adds research track

DVCon Europe is expanding coverage into research on design verification for its 10th conference later this year.
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April 4, 2023

Curvilinear layout looks to wider adoption with mask speedups

Nvidia's move into software aimed at mask production and EDA looks to be part of a wider shift to improve yields.
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March 30, 2023

SEMI predicts strong 300mm growth to 2026

SEMI predicts 300mm capacity to grow to almost 10,000 wafers per month in 2026, up from 6,500 in 2021.
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February 28, 2023

Imperas and Synopsys team on RISC-V debug

Imperas is integrating its ImperasDV verification IP with the VCS simulator and Verdi debug tools.
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January 18, 2023

Accellera forms CDC working group and takes security standard to IEEE

Accellera has formed a clock-domain crossing working group and has also passed its security-annotation standard to the IEEE.
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