Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
Mentor Graphics has launched Calibre xACT, a tool that uses deterministic algorithms to extract parasitics from complex finFET and other nanometer processes.
Cadence Design Systems has launched an analog simulation tool designed to speed up the characterization of mixed-signal macros that can then be used to create the Liberty representations needed for full-chip signoff.
Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.
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