soc signoff


June 10, 2015

SoC verification ‘should use software more’

Verification of SoCs can't be done by adapting IP-level strategies - it'll take a much greater interaction with software, and the use of a shared language
April 22, 2015

Mentor tool streamlines multi-corner parasitic extraction

Mentor Graphics has launched Calibre xACT, a tool that uses deterministic algorithms to extract parasitics from complex finFET and other nanometer processes.
October 28, 2014

Cadence tool automates library creation of analog macros

Cadence Design Systems has launched an analog simulation tool designed to speed up the characterization of mixed-signal macros that can then be used to create the Liberty representations needed for full-chip signoff.
September 5, 2013

Real Intent CEO Prakash Narain on moving from RTL to SoC sign-off

Prakash Narain of Real Intent on SoC sign-off, static verification, interoperability, predictability, ROI and more.

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