Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
X-Fab is using IHP technology to add a 130nm silicon germanium process to its offering.
The system-in-package and module trends in system design promote bringing together physical (DRC) and electrical (LVS) verification.
Equivalence checking supports the efficient reuse of designs that reside on out-of-date silicon but remain valid in their own right.
5G IC designs have needed aggressive innovation across many elements and more use of FD-SOI that both pose parasitic extraction challenges.
Learn how one of the leading tool vendors addresses the security of its products and customer data through a ground-up cybersecurity strategy.
Intel's Pathfinder for RISC-V is intended to boost the use of the architecture among a wider range of SoC design teams.
Imperas Software has published an open-source functional-coverage library for RISC-V cores.
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
As the project that funded OpenRoad draws to a close, experts pondered its wider future at the 59th DAC.
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