January 4, 2023
The choices for heterogeneous integration are falling into three main families, demonstrated by A*Star at IEDM 2022.
December 9, 2022
Adding an MOL layer that takes advantage of a self-aligned pitch-splitting technique and a rotated layout could cut standard-cell height to 4T.
November 21, 2022
Aside from the keynotes and technical papers, the networking at an event like DVCon Europe provides a way to keep open-source EDA on the road.
November 15, 2022
Real Intent has developed a tool to check design and the potential for circuits to glitch.
November 14, 2022
Semiwise has developed transistor models for the GlobalFoundries 22FDX that cover operation at cryogenic temperatures.
October 25, 2022
DVCon Europe's keynotes will examine verification issues in connected cars and 5G networks.
October 17, 2022
At IEDM, TSMC is at the top of several papers that examine how 2D materials might be put into action as successors to silicon, alongside work from a variety of institutions on power integration and thermal management.
September 27, 2022
Tessent Multi-die extends the capabilities of the DFT suite in line with new standards intended to enable widespread adoption of interposer and stacked die strategies.
September 15, 2022
Cadence has brought the inputs for its AI-driven tools under the umbrella of a big-data collection platform and added functional verification to the list of products that use machine learning.
September 14, 2022
X-Fab is using IHP technology to add a 130nm silicon germanium process to its offering.