February 1, 2024
Cadence has introduced a platform for performing thermal and thermal-stress analysis of subsystems, from 2.5D and 3DICs to PCBs and complete electronic assemblies.
January 12, 2024
Workshops on portable stimulus, functional safety, verification of RISC-V processors, and design with chiplets and large language models will feature at the upcoming 2024 DVCon US.
December 27, 2023
The two best papers at the recent DVCon Europe underlined two of the issues that now face chip-implementation teams: efficient flows and reliability.
December 22, 2023
Shifting to low-carbon generation for electricity would do much to cut the carbon footprint of semiconductor processes according to work shown at this year’s IEDM.
December 18, 2023
At IEDM, CEA-Leti described a process that avoids the thermal problems of implementing CMOS transistors in the metal stack using monolithic integration.
December 5, 2023
Start-up launches platform on path to the specification, emulation and simulation of large chiplet-based designs.
December 4, 2023
EMA Design Automation to launch sister company, Accelerated Designs, to help clients streamline processes, cut manual effort, and connect data.
November 30, 2023
Solido discusses how it has leveraged AI for SPICE level efficiency and the benchmarks it has used.
November 20, 2023
What are your options and what is one of the latest simulator features that helps streamline your build?
November 20, 2023
South Korea's leading research institute has built a reusable flow for lower power petaflops-performance AI.