This year’s IEDM features a number of papers that seek to drive down the size and boost the performance of image sensors.
The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.
Chiplet-based 3DIC designs present new challenges for flows that integrate tasks from design exploration to physical verification.
Accellera ’s board of directors has approved the version 2.1 of the Portable Test and Stimulus Standard.
From tutorials to technical papers to special 'diamond' sessions, Tessent features large at ITC 2023.
Tessent RTL Pro allows wrapper cells and x-bounding logic to be inserted earlier in designs.
MachineWare has expanded its portfolio of high-speed instruction-set simulators to the Arm Cortex-A and -M architectures.
Vertical integration is one of the major focus areas at the upcoming IEDM conference, both in terms of transistors and the multiple channels that will go into them.
Siemens and CEA-List have signed a deal under which the two organisations will research the combination of digital-twin and AI.
DVCon Europe has announced its two keynote presentations, focusing on energy-efficient high-performance computing and machine learning.
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