The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
System Technology Co-optimization raises various SI, PI, thermal, mechanical and warp risks due to its use of advanced packaging. Early-stage prototyping mitigates them.
Advanced packaging requirements from foundries and OSATs pose stringent challenges. A new paper describes three ways of satisfying them.
At December's Design Automation Conference, AMD senior vice president Sam Naffziger provided more insights into the chipmaker’s use of chiplet-based design and manufacture.
Siemens has refreshed its collaboration with PDF Solutions with the aim of using test data and other sources to provide actionable information to improve device yield.
Imperas has put together a suite of tools to verify that custom RISC-V processor cores remain compatible with the common infrastructure behind the open-source instruction set.
Breker will highlight its latest work on stress-testing processor, storage and I/O architectures during DAC 2021 this week.
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