Cadence has used machine-learning techniques originally developed for its Cerebrus tool to build software that can speed up multiphysics analysis.
VLSI Symposium 2022 will show the rapid development taking place in oxide-based replacements for traditional DRAM cells as well as the emerging area of memory-based low-power machine learning.
Recognizing the 75th anniversary of the transistor in December, the 68th IEDM has taken on the theme of looking at “transformative devices to address global challenges”.
Real Intent has extended the fault coverage of its Meridian DFT static sign-off tool with improvements to the reporting of issues and the ability to track down root causes.
DAC returns to San Francisco in July for its 59th year as a purely in-person event.
DVCon Europe will be held as a live event in Munich in early December.
The NVMe 2.0 specification has introduced two namespace options that boost SSD performance while optimizing storage life.
Nvidia says it will support the UCIe chiplet interface standard once it has "stabilized" while opening up its latest form of NVLink to other companies.
A panel at DVCon argued too much of a focus on point tools coupled with challenges with interoperability and cross-industry cooperation is hindering the ability of SoC teams to design and verify complex products.
Synopsys R&D vice president Manish Pandey described the ways in which the tools supplier has harnessed machine learning so far to gain speedups and improvements in coverage.
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