Imperas releases RISC-V coverage library as open source

By Chris Edwards |  No Comments  |  Posted: August 3, 2022
Topics/Categories: Blog - EDA, IP  |  Tags: , , ,  | Organizations: ,

Imperas Software has published an open-source functional-coverage library for RISC-V cores for use with SystemVerilog-based environments.

The initial release is for the RV32IMC and RV64 core profiles but other ratified extensions are under development and will also be released as part of the riscvOVPsimPlus package, which includes the company’s free-to-use single-core simulator. The company said it has taken the position that the rapid growth in RISC-V adoption and many new teams now undertaking a complex RISC-V processor verification task for the first time, the emerging RISC-V verification community has an urgent need for quality verification IP from a reliable source.

Imperas has developed these libraries over time to support multiple customer projects and users of the company’s commercial tools, such as ImperasDV.

“Functional coverage is fundamental to all modern processor verification plans; it marks the progress to project completion and release for prototype manufacture,” said Allen Baum of Esperanto Technologies and chair of the RISC-V International architecture-test special interest group. “The release of the Imperas SystemVerilog functional coverage library with a permissive free-to-use license will now benefit all RISC-V verification teams and complements the work of the RISC-V International Architecture Tests SIG.”

Simon Davidmann, CEO at Imperas added, “The open standard ISA of RISC-V provides great flexibility for innovation in the design of modern processor implementations. With all the configurability offered by the standard extensions and implementation options, plus users-defined custom features, the total scope of the RISC-V verification effort cannot be understated. Through our experience working with some of the most sophisticated customer designs we recognize the usefulness of ready-to-use SystemVerilog Verification IP that allows developers a solid foundation on which to build a successful [verification] plan.”

The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, latest test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is now available on OVPworld at

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