October 31, 2023
Accellera has published for public review version 0.1 of a standard designed to help pass clock-domain crossing information between EDA tools.
August 3, 2022
Accellera is on the first stage of setting up a working group to create a standard for exchanging information on clock domain crossing checks.
March 27, 2019
Siemens PLM strategy VP Stefan Jockusch will keynote on digital twins in the automotive sector at next month's conference in Shanghai.
February 11, 2019
DVCon USA is coming soon. Mentor's 2019 involvement includes a keynote from parent Siemens and a tutorial on managing your formal verification processes.
May 16, 2017
Cadence has added two apps to its JasperGold lineup that handle clock-domain crossing and linting.
January 20, 2016
A look at techniques to trap complex errors caused by signals crossing clock, reset and power domains is the focus of this upcoming webinar
May 5, 2015
New version of Vivado adds verification features and speed, extends Zynq support
June 3, 2014
Synopsys adds formal, static, clock-domain crossing, and low-power checking to verification engineers' toolbar