x propagation

March 9, 2018

DATE 2018 preview: Mentor

DATE highlights for Mentor include a 90-minute workshop on achieving functional safety for autonomous driving.
May 2, 2017

Wally Rhines looks beyond ‘endless verification’ to the system era

DVCon China saw Mentor's chairman and CEO give a typically thorough keynote on the evolving challenges for verification.
July 22, 2014

Real Intent puts the accent on debug with new Ascent IIV release

More than 20 new features and improvements are added to the static functional tool.
Article  |  Topics: Product, RTL, Verification  |  Tags: , , , , ,   |  Organizations:
June 2, 2014

Real Intent’s Pranav Ashar on converging design and verification

Verify early and simulate as little as possible - the idea is familiar but how do you get there?
March 26, 2014

Real Intent’s Ascent XV at the ‘fuzzy’ boundary between design and verificiation

Upgrade to Ascent XV X-propagation and reset optimization tool claims 10X runtime gain, deeper reporting, further integration with Verdi and more.
Article  |  Topics: Blog - EDA, - Verification  |  Tags: , , , , ,   |  Organizations: ,
January 14, 2014

Cadence updates Incisive with formal, CRV, wreal additions

Cadence's Incisive 13.2 verification environment includes new formal and constraints engines, X propagation checks, and further real-number model support.
Article  |  Topics: Blog - EDA  |  Tags: , , , , ,   |  Organizations:
September 19, 2013

Real Intent updates X verification tool

Updated tool checks for correct design initialization, as well as managing X optimism and X pessimism at RTL or netlist level.
Article  |  Topics: Verification  |  Tags: , , ,   |  Organizations:
July 8, 2013

Real Intent links tools to Synopsys flows through in-Sync program

Real Intent has linked its key tools into Synopsys' VCS Verilog simulation and HDL Compiler tool flows.
Article  |  Topics: Product  |  Tags: , , ,   |  Organizations: ,
October 17, 2012

Mentor extends Questa with formal coverage checks

New features provide enhanced formal checking analysis, code coverage closure and extended clock domain crossing analysis.


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