Simulation suite automates the largely manual process of validating more than 25 SerDes protocols.
Cadence Design Systems has released a set of ten verification IP packages intended to support a new crop of standard protocols.
Synopsys delivers reconfigured PHY IP to support reversible USB Type-C connector.
Thunderbolt speed to double to 40GBit/s, cheaper ownership for consumers, proprietary plug dumped in favor of USB-C as Intel looks to reinvigorate tech.
UltraSoC has added the ability to employ a USB 2.0 port instead of JTAG as the main debug access point on SoCs that use the company’s UltraDebug technology.
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Test and Verification Solutions has expanded its library of verification IP to cover protocols in MIPI, memories, serial IO and communication.
Cadence Design Systems has decided to buy Poland-based IP developer Evatronix as part of a plan to round out its portfolio of interfaces for SoC designs.
Cadence Design Systems is to buy Cosmic Circuits Private Limited, a developer of analog and mixed signal intellectual property (IP) cores.
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.
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