Achieving functional coverage for the increasing number of designs realized in multiple languages is challenging, particularly when they begin at the high level of abstraction offered by System C. Currently, no agreed comprehensive standard exists for the process of determining that a multi-language design is acting as expected and that its content has been sufficiently covered.
Siemens EDA has released a technical paper first presented at this year’s DVCon which, while noting that broader process standardization will ultimately be needed, there are already ways of approaching the task that stretch across SystemC and Transaction Level Modeling through UVM Connect (UVMC) and SystemVerilog where gaps currently exist.
“I have come up with a familiar solution of utilizing functional coverage usage by exporting them from SystemC to SystemVerilog each time a sampling event is called on the SystemC side,” explains author Vishal Baskar.
The paper is structured in three main parts.
First, some background on coverage analysis and SystemC modeling using UVMC, the library that already provides TLM 1.0 and 2.0 connectivity as well as object passing between SystemC and SystemVerilog-UMV models and components. UVMC is a key enabler for the strategy the paper discusses.
Second, a detailed descirption of Baskar’s proposed workflows, including examples, coding and results. Two strategies are explored. “One uses a generic payload and extracts coverpoint data from that and the other by using a packet that contains address, data, etc.,” he explains, “and the other uses a custom template specialization class that consists of UVM’s ‘do_pack’ and ‘do_unpack’ methods.
Finally, there is a summary of the results achieved and suggestions for future work.
‘Do not forget to get your SystemC code covered with UVMC‘ is available for immediate download.