IP implementation variety drives latest partnerships

By Paul Dempsey |  No Comments  |  Posted: March 9, 2016
Topics/Categories: Digital/analog implementation, Blog - EDA, IP, - Product, Tested Component to System, Verification  |  Tags: , , , , , , , , , , , , , , , , ,  | Organizations: ,

Over the last decade, the variety of intellectual property (IP) implementations has proliferated. Ever fewer licensees simply drag-and-drop a processor core into a design before heading out to market. Tweaks – be they subtle or major – reflect the continuing push for differentiation, greater familiarity with third-party IP and the need to integrate more functionality.

Then there is the need to ‘shift left’, to move tasks up the design flow thereby reducing the risk of late-stage ECOs and shortening time-to-market.

These dynamics lay behind a series of collaborations announced by Mentor Graphics during the last year. For example, Mentor relationship with Imagination Technologies now covers the use of its Codelink debug offering for the Veloce emulator across the full-range of MIPS CPUs.The latest agreement, signed in February, established and extended the company’s relationship with another leading core provider, ARM.

IP in every flavor

The ARM agreement is a wide-ranging, multi-year subscription and gives the tool vendor an inside track on ongoing development of the ARMv8-A and ARMv7-A architectures, Mali graphics processors, CoreLink system IP, Artisan physical IP and ARM POP IP for accelerating implementations. It specifically addresses verification-to-back-end challenges as met by tools such as Questa in simulation, Veloce in emulation, RealTime Designer in physical synthesis, Olympus-SoC in place and route, and Tessent in both memory and logic BIST as well as compression.

“We have had early access to ARM v7 and v8 before but chiefly through customer engagements,” says Jean-Marie Brunet, director of marketing for Mentor’s emulation division. “Those would be tied to the specific implementations they were working on.

“We now have generic access with two important results. First, we get access to the technology at the same time as the customer, even before. Second – and this is the game changer – that means we can start our own R&D earlier so that, as soon as the customer has developed an implementation of an ARM core, the tools are there. They have already been fine-tuned to deal with the latest ARM technology, across the full range of IP and its potential uses.”

Brunet adds that the extended ARM agreement is something Mentor’s customers themselves have been seeking.

“We’ve been working with ARM for years but the feedback from this agreement has been particularly positive. It doesn’t affect the closeness of our existing relationships with customers; what this does is take important steps in reducing risk and accelerating design,” he says. “Where a customer knows this kind of relationship is in place, it particularly reduces risk for them in implementing third-party IP from that source.”

Another driver for both deals has been the growing use of emulation, an EDA segment where Veloce is a market leader but faces competition from Cadence Design System’s Palladium product and Synopsys’ Zebu offering. Moreover, the trend toward wider, enterprise-based emulation has inevitably led to a greater focus on the accompanying tool infrastructure, particularly the quality of models.

As Brunet notes, “You need to build out the ecosystem aggressively, and that means you have to get deals like this in place.”

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