IP choice drives SSD controller design
Two-year-old design house make IP choice to use Synopsys DesignWare to build an enterprise SSD controller from scratch.
DDR
Cadence ports IP and qualifies tools for 28nm FD-SOI
Cadence Design Systems has developed two sets of IP aimed at the 28nm FD-SOI process developed by STMicroelectronics and qualified tools for the process.
Visual timing tool focuses on high-speed PCB signals
Cadence Design Systems has developed a visual timing analyzer for Allegro that tunes signals used by high-speed protocols such as DDR4, PCI Express, and SATA.
Mentor updates HyperLynx for faster boards, more rules checking
Mentor's HyperLynx gets speed and accuracy enhancements, as well as more embedded help, to speed up fast board design
Synopsys verification IP launch has bite
Synopsys has rolled out its SystemVerilog-based verification IP portfolio for a bunch of interconnect standards – and built in support for all the three major verification methodologies.
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