Engineering consultancy Tessolve is bringing its Verification Futures conference, which has run for more than a decade in the UK, to the US with an event scheduled for mid-September in Austin, Texas.
Taking place at the Austin Marriott South on September 14, 2023 with the option of remote video access, Verification Futures (USA) is a one-day event that will include talks on a range of areas in functional verification, ranging from RISC-V processor design to safe and secure control systems.
One of the features of the format developed by Tessolve is to have user talks that focus on issues that verification engineers face in their day-to-day work. At this event, Alex Duhovich, methodology lead at Ericsson, will talk about the communication equipment company’s strategy for verifying products with a long operational life. Vivek Vedula, head of methodology architecture and development at Arm, will provide a keynote on safety and security challenges in hardware IP development.
Intel SoC design engineer will talk about the verification strategy used in the creation of the company’s 12th generation “Alderlake” processors. The validation challenge for this design that couples performance and efficiency cores spanned both pre-silicon and post-silicon phases and called for an overhaul to the techniques used by the team: ranging from updating existing test generators all the way to developing new testing methodologies.
The 17 talks on the day will include two training sessions provided by Doulos, both looking at ways to incorporate formal verification into projects and how to deal with non-determinism in large state spaces. Another focus of the conference, in addition to automating and improving testbenches, is on bringing analog/mixed-signal into UVM-based verification environments.
The event is sponsored by Cadence Design Systems, Imperas, Breker Systems, and Doulos with free registration for both physical and virtual access through Eventbrite.