How to cut verification time with VIP

By David Aerne and Ankur Jain |  No Comments  |  Posted: November 2, 2015
Topics/Categories: EDA - Verification  |  Tags: , , , ,  | Organizations: ,

This article shows practical ways to use verification IP for greater productivity with specific code examples from Mentor Graphics’ Questa platform.

Verification IP (VIP) addresses many of the inherent challenges in verifying today’s complex designs, but must meet certain requirements. It needs to be proven, provide checks that ensure protocol compliance, include a comprehensive compliance test suite, and enable the collection and analysis of coverage data. It should also be straightforward to instantiate, configure, and exercise, minimizing the time to productive verification.

This article explores these qualities and illustrates their importance by way of reference to the Questa Verification IP (QVIP), a part of the Mentor Graphics Enterprise Verification Platform, and its EZ-VIP features. In particular, it considers the VIP components available for the PCI Express (PCIe) and ARM AMBA 4 AXI standards.

Verification IP integration

The first step in deploying VIP is its integration within the test bench. A decision needs to be made regarding what the VIP will model. In our example, should it model a PCIe End Point (EP) or Root Complex (RC)? And should it do so at the MAC or PHY level? Or perhaps it should be deployed in monitor mode, providing protocol compliance checks and functional coverage without driving or responding to stimulus?

Once this decision is made, the hookup requirements are known and the interface can be instantiated and wired-up.

QVIP provides wrapper modules specific to each different use case. They ease the instantiation and port connection process. The modules instantiate the QVIP interface and provide, in the case of PCIe, for per-lane signals. Users simply deploy the modules and make the connections to the device-under-test (DUT). You do not need to explicitly instantiate a QVIP interface or set it within a UVM configuration database; that is done inside the wrapper module.

The wrapper modules in Figure 1 show PCIe QVIP for connecting a DUT via various interfaces.

Figure 1: PCIe QVIP wrapper modules (Mentor Graphics)

Figure 1: PCIe QVIP wrapper modules (Mentor Graphics)

Verification IP configuration

The next step is configuration of the VIP. As QVIP is fully featured for each protocol specification, there are numerous configuration options and parameters that may need to be specified. QVIP provides a simple way of implementing these using a protocol-specific agent.

The agent has an agent descriptor structure — or ‘struct’ — that lets the user specify the most common configuration values. This jump starts productive verification. A simple example would be where the descriptor specifies whether the QVIP should model an RC or an EP. You save time by using this approach because there is no need to write UVM code to create analysis ports. Moreover, the user can specify which types of coverage are collected and whether transactions and symbols are logged.

Usage examples for ‘struct’ are shown in these two code snippets (Figures 2 and 3).

Figure 2. Code snippet (a) for ‘struct’ descriptor (Mentor Graphics)

Figure 2. Code snippet (a) for ‘struct’ descriptor (Mentor Graphics)

Figure 3. Code snippet (b) for ‘struct’ descriptor (Mentor Graphics)

Figure 3. Code snippet (b) for ‘struct’ descriptor (Mentor Graphics)

Link training and enumeration for verification IP

Your next steps toward bringing up a PCIe test bench are link-training and enumeration. These are achieved in our example by running ‘pcie_bring_up_sequence’. The sequence includes the following functionality:

  1. Initialization of the configuration space.
  2. Automatic training of the link to the desired speed.
  3. Waiting on the DL_ACTIVE state to indicate successful link-up.
  4. If QVIP is configured as RC, performing enumeration by starting the ‘pcie_tlp_ bus_enumeration’ sequence (This enumerates the PCIe fabric using the default BAR configuration).
  5. Generating completions by starting ‘pcie_completer_sequence’ (This runs in the background and sends completion responses to the DUT for requests received by the QVIP).

The code snippet in Figure 4 shows how easy it is to perform the complex PCIe functionality shown above by starting this bring-up sequence in the run phase of a test.

Figure 4. Code snippet for ‘pcie_bring_up_sequence’ (Mentor Graphics)

Figure 4. Code snippet for ‘pcie_bring_up_sequence’ (Mentor Graphics)

Quick starter kits for verification IP

Most SoCs include third-party IP. QVIP provides customized quick-start kits pre-configured for standard IP. Kits cut the time needed to install, instantiate, configure and bring up VIP to less than one working day.

For PCIe, most designs are endpoints. So, kits are provided for a use-case where QVIP is RC with the DUT as EP. This integration flow can be summarized in a few quick steps and is shown after in Figure 5.

  1. DUT TB connections: Each kit provides a top level module that shows how to connect the PCIe design IP to a QVIP wrapper module. Separate kits are available for serial and pipe connections.
  2. QVIP configuration: Each kit contains a configuration policy class that includes the settings needed to bring up the PCIe design IP during link-training. These should not be edited. The EP configuration policy is designed for the test class of the user’s testbench and contains a method called ‘configure()’ that is used for the PCIe QVIP configuration object.
  3. Link-training and enumeration: The link-training can be the most problematic part of the process, but the settings in the kit configuration policies mitigate this risk. Once the link is trained, enumeration is straightforward and can also be accomplished using the generic ‘pcie_bring_up_ sequence’ explained above.
Figure 5: PCIe quick-starter kit flow (Mentor Graphics)

Figure 5: PCIe quick-starter kit flow (Mentor Graphics)

Application verification with VIP

The user can now begin to verify a particular application. QVIP provides a comprehensive test suite library of sequences and sequence items for different packet formats, complex protocol flows, error injection, coverage, and compliance tests.

However, there is always a need for easy-to-use sequences especially during early verification. All protocols have a common objective to transfer data between two ends, and the simplest transactions can be represented as reads and writes. QVIP provides task-based sequences to perform the read and write APIs. These are described in the following section.

Easy-to-use read/write APIs for verification IP

QVIP provides read/write APIs that are generic in nature and thus protocol agnostic – the same interfaces are available for various AMBA protocols (e.g. AHB, AXI3/4, ACE, and CHI). Simple sequences are also available to perform reads and writes for different PCIe memory, configuration and I/O requirements.

Figure 6 lists the generic APIs available for the AMBA family.

Figure 6: Generic APIs for AMBA (Mentor Graphics)

Figure 6: Generic APIs for AMBA (Mentor Graphics)

A read/write API conducts basic reads and writes as though a program is running on a processor. It provides a generic protocol-agnostic interface, letting the API sequence implementation choose the most appropriate bus transaction and corresponding attributes. These API methods have only a handful of simple arguments: address, data and ID with no direct dependency on bus-specific attributes. Bus-specific attributes are determined by less frequently changing configurations such as the ‘address map’ and ‘attributes API’. The code snippet in Figure 7 shows the generic function prototype.

Figure 7. Expressing the generic function prototype (Mentor Graphics)

Figure 7. Expressing the generic function prototype (Mentor Graphics)

Then in Figure 8, we write the given ‘data’starting at address ‘addr’.

Figure 8. Writing the given ‘data’ (Mentor Graphics)

Figure 8. Writing the given ‘data’ (Mentor Graphics)

The optional ‘id’ identifies a transaction stream. Writes and reads with the same ‘id’ will finish in order of execution.

Use of read/write APIs with verification IP

QVIP provides a generic base class sequence (‘rw_api_ base_seq’) and protocol-specific sequences (e.g., ‘axi4_master_seq’). The protocol-specific sequences are derived from the generic base class and provide appropriate read/write API functionality.

The code snippet in Figure 9 demonstrates an extension of a ‘axi4_master_seq’ to perform desired read and write operations.

Figure 9. Extension for read and write operations (Source: Mentor Graphics)

Figure 9. Extension for read and write operations (Source: Mentor Graphics)

Delivering productivity with verification IP

EZ-VIP features showcase the ability to rapidly deploy QVIP and quickly start productive verification of complex SoCs. These include easy-to-use connectivity modules, one-stop configuration, quick-starter kits, and portable utility sequences for use whether verifying at the block level or within an end-to-end test bench which contains multiple protocols (Figure 10).

Figure 10: Typical testbench for a PCIe DUT (Source: Mentor Graphics)

Figure 10: Typical testbench for a PCIe DUT (Source: Mentor Graphics)

Alongside its ease-of-use, Questa VIP provides monitors to ensure protocol compliance as well as analysis components such as a scoreboard and coverage collectors. Comprehensive test suites and functional test plans allow the verification team to track and achieve coverage goals. The building blocks are written in unencrypted SystemVerilog and encapsulated within a ready to be deployed UVM environment.

Questa VIP provides a fast track to verification productivity via its EZ-VIP set of features as well as all the other tools necessary for exhaustive verification of complex protocols such as PCIe.

Further information

If you want to learn more about using UVM-based verification IP for protocols such as PCI Express, MIPI CSI, and DSI, this webinar provides a great deal more useful information.

About the authors

David Aerne and Ankur Jain are Verification Technologists at Mentor Graphics

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