October 25, 2023
This year’s IEDM features a number of papers that seek to drive down the size and boost the performance of image sensors.
September 19, 2018
Cadence has launched an AI processor using an designed to take advantage of the sparse structure of typical deep neural networks.
July 30, 2018
IP supplier FotoNation has decided to embrace the use of high-level synthesis in the creation of cores for smartphones and other high-integration, low-power systems.
April 11, 2018
Cadence Design Systems’ Tensilica division has launched a variant of its Vision P6 processor core to tackle embedded designs that need to run a mixture of imaging and deep learning-type algorithms.
February 13, 2018
By the middle of this year Arm intends to deliver a processor designed specifically for deep-learning pipelines in edge devices, to capitalize on a move away from cloud computing for image and voice recognition.
January 5, 2018
Ceva has developed its first processor architecture aimed squarely at deep learning.
December 7, 2017
ST has tweaked its standard HLS flow for ISPs to meet the requirements of ISO 26262
May 1, 2017
Cadence has stripped out some of the image-processing functions of the Vision P6 and boosted the number of execution units to build a DSP aimed at deep learning.
July 12, 2016
EEMBC has turned its attention to heterogeneous computing with plans to create a new set of benchmarks.
October 22, 2015
IP supplier CEVA has made a development platform intended to speed up the prototyping of IoT and similar devices based on its TeakLite-4 DSP core.