Tessent speeds ‘shift left’ drive for test at RTL
The latest ‘shift left’ innovations from Siemens EDA address design-for-test logic. Tessent RTL Pro allows users to analyze opportunities and needs for it and then insert test points, wrapper cells, and x-bounding logic earlier in the design flow.
As with other shift-left innovations, the goal is to advance test and verification tasks that have historically waited until later so as to catch bugs and opportunities for enhancement earlier while reducing time-to-market.
Figure 1. Tessent RTL Pro allows earlier logic insertion for test points, wrapper cells, and x-bounding logic.
Siemens says the latest addition to Tessent has been designed to retain the character and look of the original RTL that is analyzed and that Tessent RTL Pro can handle complex Verilog and SystemVerilog.
The new tool is also compatible with third party flows.
It has previously been possible to insert some test features comparatively early in a flow, but for those covered by Tessent RTL Pro, an advance in design editing capabilities has been necessary.
“With the ability to analyze and insert wrapper cells, x-bounding logic, and VersaPoint test points at the RTL stage of design, customers can now extend their shift-left initiatives by substantially enhancing the testability of their designs,” said Ankur Gupta, vice president and general manager, of the Tessent division.
With the new editing features, Tessent RTL Pro is able to go in and modify parts of the RTL previously considered beyond reach while maintaining the integrity that designers demand.
