Catapult HLS integrates eFPGA IP for faster development

By TDF Editor |  No Comments  |  Posted: April 2, 2019
Topics/Categories: Blog - EDA, - HLS, Blog - IP  |  Tags: , , , , ,  | Organizations: ,

Mentor, a Siemens business, is looking to extend the configurability options available from high-level synthesis (HLS) through a collaboration with Menta SAS, a provider of customizable embedded FPGA (eFPGA) IP.

The integration between Mentor’s Catapult HLS tool family and Menta’s IP and accompanying Origami programmer will, the companies say, allow design teams to change eFPGA configurations at any stage of development.

Menta’s IP allows engineers to specify the size and number of embedded logic blocks (eLBs), global clocks, memory, ALUs, and interfaces as required for any application at any process node. Menta’s eFPGA fabric also supports third party IP and memory blocks.

The rapid evolution seen in many AI-based designs, particularly those in spaces such as machine vision that are well suited to HLS, makes the extra flexibility offered through Menta’s eFPGA IP very suitable. Such designs can go through multiple iterations as algorithms are refined and the optimal hardware-software balance is determined through ‘what if’ exploration.

The integrated Catapult and eFPGA design and development environment is available now. More information is available here.

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