The modelling track at IEDM 2012 showed how germanium could be used in 14nm finFETs. Other work focused on tunnel FETs and analyzing MEMS using Spice.
finFETs are vital to the next generation of CMOS processes from Intel, TSMC and others. How will process issues including bulk vs SOI substrates, density limitations, thickness control, and planar device integration affect their practical implementation?
Advanced SOI devices with hybrid channel materials may challenge the finFET's future dominance, says IBM
Intel finFET family grows to support SoC use, as TSMC boosts p-channel performance with germanium
GlobalFoundries has confirmed its 14nm process as the one that will see the foundry introduced finFET-based transistors, claiming that its approach is optimized for mobile devices
The president and co-CEO of Synopsys provides his take on the mounting influence of software and physical effects in the creation of SoCs.
You want finFETs with different threshold voltages on the same SoC? Forget what the FD-SOI guys tell you: it's possible. At least with a certain amount of performance loss, say IBM and GlobalFoundries.
FinFET or trigate structure provide a number of degrees of freedom in design in the battle against DIBL – and one of those dimensions is doping, Professor Tsu-Jae King Liu explained in a course ahead of the 2012 VLSI Symposia this week.
What are the chances that FD SOI will become a mainstream process for future nodes?
A startup has analyzed the shape of Intel's fins and found the process is not quite as well-behaved as circuit designers would perhaps like.
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