FD-SOI processes lead to double-decker monolithic 3D

By Chris Edwards |  No Comments  |  Posted: December 18, 2023
Topics/Categories: Blog - EDA  |  Tags: , , ,  | Organizations:

CEA-Leti demonstrated at this month’s International Electron Device Meeting (IEDM) a process that avoids the thermal problems of implementing CMOS transistors in the metal stack using sequential, monolithic construction rather than bonded wafers.

The bottom tier consisted of a 28nm fully depleted silicon-on-insulator (FD-SOI) active layer with four metal layers for back-end-of-line (BEOL) interconnect. Once the metal layers were in place, the wafer was returned to front-end processing where a doped polysilicon plane was deposited to provide backplane suitable for backbiasing a second tier of CMOS devices as well as elements of image-sensor pixels.

Although researchers have managed to construct FDSOI devices that will survive a temperatures of up to 500°C after their processing has completed, it has proven to difficult to reduce temperatures far enough to create monocrystalline CMOS transistors, with a gate length of around 65nm, above them in the metal stack. In the process disclosed at IEDM, the CEA-Leti team was able to restrict temperatures to a maximum of 500°C, and these were only required for two hours through the use of ultraviolet laser annealing. Once the upper-layer devices were in place, processing continued for six further layers of metal interconnect. They used compressive strain to improve the performance of both the n- and p-channel devices.

The team checked connectivity and behavior using ring oscillators constructed from alternating top and bottom transistors connected by bias as well as layer-specific oscillators.

The pixel elements were split between the top and bottom layers, with a 3T-pixel constructed using standard implants used on FD-SOI processes. The top tier contained flip-flops and a latched comparator used to inject a hole packet to prevent full saturation. Though it serves as a proof of concept, the researchers said a commercial implementation would need a denser FD-SOI technology on the top layer. However, one option might be to use the bottom layer for conventional pixel construction and then use the top layer for other functions.

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