backside power delivery

The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.

Cadence has agreed to work with Intel Foundry Services on IP and flows for the 18A process, which will include backside power delivery and nanosheet transistors.

The IEEE Symposium on VLSI Technology & Circuits switches back to Honolulu for its 44th year in the summer of next year and has issued its call for papers, with a deadline of early February for contributions.

Backside power delivery could lead to improvements in chip density and more straightforward place-and-route phases according to work presented at this year’s VLSI Symposium.