VLSI to explore vertical device changes and 3nm finFET
The upcoming VLSI Symposium will examine progress in using backside contacts and 3D structures to improve density and speed as well as continuing improvements to finFET processes.
power analysis
Cadence combines ML techniques for power signoff
Cadence has linked several machine-learning approaches to build a tool that is designed to speed up the detection and diagnosis of on-chip power-integrity issues.
DAC 2017 preview: Baum
Start-up Baum is co-located with Verific at DAC 2017 and will demonstrate its soon-to-launch power analysis and modeling software.
Webinar discusses SoC security, area, and power trade-offs
SoC security strategies, costs and trade-offs are analysed in this detailed webinar.
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